It's Evolution, Not Revolution, For PCB Tools

Feb. 2, 2006
To conquer ever-stiffer challenges, pc-board design tools must perpetually evolve-particularly in the high-speed signal realm.

When it comes to pc-board (PCB) design, change isn't necessarily radical. Though IC design tools must keep pace with fast technological changes, tools for the PCB designer tend to embrace change in a more evolutionary style.

That's not to say the PCB designer's world is peaceful and calm. Thanks to innovations such as multigigabit serial data-streaming technologies like serializers/deserializers (SERDES), PCB designers face extremely difficult signal-integrity challenges. If their toolsets aren't up to speed (pun intended), they'll likely struggle to meet timing requirements.

All of the above—combined, of course, with the ongoing trend toward higher pin counts on ICs—creates an environment where PCB designers must have the right tools for the task at hand. Even still, that task may catch you by surprise. In this report, we'll survey some of the challenges facing PCB designers and examine how today's crop of design tools handles them.

THE NEED FOR SPEED "PCB design has become a highly constrained, complex system design process," says Werner Rissiek, Zuken's European general manager of engineering. "It's definitely not simply about artwork any longer. It's engineering all the way through from specifying your product schematics to floorplanning, layout, and manufacturing."

Today, extremely high signal speeds drive much of that need for engineering throughout the board-design process. Modern processors require modern buses, and those buses carry very fast signals. "Once clock rates hit 300 or 400 MHz, you start to really struggle with signal integrity," says John Isaac, director of market development for Mentor Graphics' System Design Division.

Migrating from parallel buses to serial data and clock transfers exacerbates the high-speed signal trend. For example, the PCI Express protocol has largely replaced the PCI bus. PCI Express replaces a parallel bus with a differential pair that transmits data and clock on the same link.

"There are two benefits to such schemes," says A.J. Incorvaia, vice president of research and development for Cadence's Allegro PCB products. "One is that you take a lot less PCB real estate to design in the links. Also, being differential, the links are somewhat immune to interference from aggressor nets. They're somewhat shielded because interference on both lines cancels out."

The design challenge is the 2.5-Gbit/s rate imposed by PCI Express. At such speeds, signals are much more sensitive to path discontinuities like vias, connectors, or long traces.

"Designing a complete interconnect is a big factor in success," says Incorvaia. "Most often, people have to simulate to figure out what the design rules are. Then, designing the interconnects based on those constraints is a challenge."

One example of a simulation tool that can handle high-speed challenges is Cadence's Allegro PCB SI 630 (Fig. 1). It simulates up to 10 kbits/s and 1 Mbit/hour on a desktop PC, which means it can run through multiple full-board simulations in a single day.

"Channel analysis is the key," says Incorvaia. "We have innovative ways to characterize the channel and simulate that in a non-traditional way."

Another speed-related issue making life difficult for PCB designers concerns memory access. Circuit designers are seeing a move from standard SDRAM to double-data-rate (DDR). Current designs mostly use DDR2 memory. With access rates of 800 MHz, though, DDR3 continues to gain favor in consumer electronics.

"When you go from DDR to DDR2 and DDR3, designers need detailed simulation to come up with the design constraints that will enable them to do layout according to those constraints," says Incorvaia. "Otherwise, you design a board and run into iterations."

Broad adoption of high-speed serial buses and advanced memory technologies forces board designers to become experts in signal integrity, and that may not necessarily be the case for many of these designers. In fact, the concerns at these speeds may go above and beyond simple signal integrity.

"High-speed considerations are changing from signal integrity, where you look at characteristics like overshoot or the delay for just one signal, to datastream verification," says Zuken's Rissiek. "Here, you are no longer interested in a single effect on a single signal, but rather multiple signals and their sequence through components. You need to ensure that the datastream is reliable. So you need eye diagrams as well as complex stimuli for analysis that reflects a real datastream on the signals."

FROM EXOTIC TO MUNDANE Some years ago, a number of what were considered "extremely exotic" board-design elements came into vogue. Since then, technologies such as blind and buried vias, embedded passive components, and flex circuitry dropped their "niche" tags. Now they're becoming part of the board designer's arsenal on a more regular basis. Thus, designers must be sure their current toolset can handle these technologies efficiently.

High-end buses, required by sophisticated silicon, once again are driving the adoption of technologies like embedded passive components. Systems-on-a-chip (SoCs) and ASICs typically containa very large number of I/Os, which need an even larger number of resistors and capacitors for both decoupling and termination purposes.

"Discretes have always been required," says Mentor Graphics' Isaac. "But now, when you get into requiring hundreds of them to support a single high-end IC, you have to consider embedding them in the inner layers under the IC versus sucking up a lot of real estate on the outer layer."

Again, it's not new technology. Rather, the technology is now coming into its own, driven by speeds, IC pin counts, and needs for smaller form factors.

A HOLISTIC APPROACH The combination of high speeds and large pin-count devices, such as FPGAs, pushes designers and EDA vendors toward taking a holistic view of the PCBs and the components they carry. The malleability that makes FPGAs such a useful tool for designers also presents a very different scenario to the board designer.

"FPGAs represent the next stage of softening of the whole design process," explains Nick Martin, CEO of Altium. "With FPGAs, you can upgrade the hardware in addition to the software. You can, for example, perform massively parallel DSP implementation after you've designed your board. So your board level process is very different. It's about doing a platform."

Altium's Designer 6.0 supports PCB/FPGA co-design. Thus, designers can fully exploit FPGAs as a system platform. One major snag for board designers, though, is that FPGA pins often are assigned without regard to board layout. In addition, the dense packaging technology in large-scale FPGAs can wreak havoc with board routing.

The concept of dynamic net reassignment embodies a key feature of Altium Designer 6.0. With this feature, FPGA pins can be swapped on-the-fly during PCB routing. The tool dynamically reallocates pre-routed subnets and swaps linked differential signal pairs.

By combining dynamic net reassignment with an automatic FPGA pin-optimization engine, Designer 6.0 enables engineers to take full advantage of FPGA pin reprogrammability to optimize board-level routing (Fig. 2). Pin changes made at board level are automatically synchronized with the FPGA design, which eliminates time-consuming manual I/O management.

It's interesting to note that IC package design is becoming increasingly PCB-like. "More of the system is moving off the PCB. We're out of single-die packages and into multiple-die packages," says Ken Mohamed, senior applications engineer at Optimal (Fig. 3).

"On the board, the difficult issues are in the interfaces between those packages and in getting power and signal to those packages. It's not just the board or package itself. You need to look at the full system, which means PCB, package, and die effects," he adds.

Optimal's tools, such as PakSI-TM, a thermal/mechanical modeling tool, and PakSI-E, a signal-integrity analysis suite, let designers model the behavior of these systems. The geometries involved are the primary factor that affects behavior, says Mohamed.

"We're seeing PCB-type topologies moving onto a different scale. And it's a range of scales. You have the PCB itself, and then the same structures on the die level," he says.

From Mohamed's and Optimal's perspective, EDA companies have made assumptions and simplifications to make the geometry issues solvable.

"Now, we're losing the ability to hold onto those simplifications as things scale down," says Mohamed. Tools like Optimal's are being called upon to simulate and analyze on a scale that's difficult to verify through comparisons with direct measurement, so it's increasingly critical for designers to be able to trust the results of those simulations.

MELDING DESIGN AND TEST Many PCB designers would stand to gain from broadened functionality in their design tools. In a joint survey conducted last year by National Instruments and Tektronix, 44% of designers said they'd benefit from connectivity between their EDA tools and measurement equipment.

The latest release of the Electronics Workbench DesignSuite embodies National Instruments' response. Version 9 of the suite seeks to break down the artificial partitions between part selection, desktop design work, and benchtop measurement by forging tight integration between version 9 of Multisim, its popular PCB simulation tool, and LabView, the company's flagship virtual instrumentation software.

As a result, designers now can use LabView to build custom virtual instruments for use within Multisim. Simulated circuits then can be driven using real-world stimulus acquired via LabView and NI's SignalExpress, a package for signal acquisition and analysis. To close the loop, simulation results are easily imported into Lab-View and SignalExpress for correlation purposes.

THE PERILS OF PLACEMENT Believe it or not, component placement is among the more vexing aspects of PCB design today. That's largely due to the fact that over the course of a system design, component netlists change many times, making for a highly convoluted and difficult-to-manage placement process. Some estimates say that it consumes as much as 50% or more of the total PCB-design cycle.

Few tools on the market automate the process of component placement on PCBs. One notable example is DesignAdvance's CircuitSpace, a 3D placement tool purported to shave up to 40% off the overall PCB cycle. According to Randy Eager, CEO of DesignAdvance, CircuitSpace employs an extended pattern-search algorithm to find a global optimum solution for component placement.

CircuitSpace operates within the Cadence Allegro PCB design flow. It appears as a pull-down menu rather than functioning as a standalone tool (Fig. 4). Allegro considers routing as it performs automatic placement based on the user's constraints.

An important factor in CircuitSpace's ability to compress placement is its cluster-definition functionality. When PCB designers perform placement, they first cluster components by connectivity and package type. CircuitSpace performs this step automatically, reducing a process that ordinarily takes days into mere minutes. CircuitSpace also makes reuse of earlier boards' sections much easier, automating the time-consuming and error-prone process of assigning reference designators.

Like many other aspects of system design, PCB design is a global affair. Design teams scattered all over the world must collaborate smoothly. To facilitate this collaboration, Mentor Graphics recently debuted its Expedition Enterprise flow for multisite, global electronics companies.

A major aspect of Expedition Enterprise is its IP management capabilities. It enables design teams to efficiently create, control, and provide access to IP on a global scale. These capabilities encompass design data, library data, and design constraints, as well as design-intent information.

Much like Altium's Designer 6.0, Mentor's Expedition Enterprise manages PCB/FPGA co-design. It includes signal-integrity verification functions and uses a correct-by-construction methodology to place and route complex boards. The package also addresses regulation compliance.

The systems emanating from global companies often are distributed globally. Expedition Enterprise helps designers keep track of country-specific directives, specifically in the Restrictions on Hazardous Substances(RoHS)/Waste from Electrical and Electronic Equipment (WEEE) areas.

This process begins at part selection. The tool can be instructed to block selection of noncompliant parts. It then follows through with guidance on other materials as well as documentation.

It's become clear where PCB design tools are headed. Now, they must evolve to fill the changing needs of designers. So far, the EDA industry seems to be up to the task.

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