# The Key To Estimating Final Chip Cost

Nov. 11, 2005
One of the bleaker urban legends has it that a latchkey kid came home from school one day to find the locks on the house changed, the family moved, and no forwarding address in sight. Perhaps IC designers who once held the key to estimating final chip cos

One of the bleaker urban legends has it that a latchkey kid came home from school one day to find the locks on the house changed, the family moved, and no forwarding address in sight. Perhaps IC designers who once held the key to estimating final chip cost can relate as they gradually discover that, in effect, the locks have been changed.

Once upon a time, because silicon was the dominant factor in all cost calculations, estimating chip cost was a simple matter of determining die size. Silicon remains a major variable in the equation, but it has become necessary to think outside the die.

As IC designs become increasingly complex, factors other than pure die size can have a huge impact on final chip cost. To generate a realistic budgetary quotation, designers should start from a simple chip-cost formula as indicated below:

Final chip unit cost = yielded die cost + package cost + test and assembly cost

Non-recurring engineering (NRE) costs should also be factored in. They will include mask costs, probe cards, load boards, wafer prototype lots, up-front and royalty-based IP costs, tool costs, engineering costs, and other one-time capital expenditures.

The key to estimating a modern IC’s final cost is to consider the interrelationships among the diverse variables. Technical decisions made early in the design flow can have huge economic ramifications. For example, should you consider a push to 90 nm and assume a \$1M mask NRE? How will that impact unit cost, power, and leakage versus the same factors associated with a 130-nm implementation? Or, you may be considering an FPGA or structured ASIC, but you may want to weigh higher unit costs against a mature, low-cost 0.18-micron process with an industry-average NRE of \$250,000. The only way to perform an effective cost/benefit analysis is to frame the question around projected volumes, and in the context of the chip’s functional requirements and the IP, tools, and engineering resources needed.

Early analysis is the best way to keep die and package costs under control. It is not uncommon to find a die requiring a package that costs three times as much as the silicon. Factors influencing package cost include die size, pin count, form factor, and power. It is also necessary to consider the impact of analog and other IP upon test time, which can add significantly to unit cost, depending on whether wafer test, package test, and burn-in testing are being performed. It is certainly preferable for designers to know about such factors earlier rather than later, when they still retain the flexibility to rethink key technical decisions.

The reason that the cost-estimation "locks" were changed is that cost has gradually evolved into an engineering problem and is no longer the sole province of the bean counters. To reach accurate final-chip estimations, cost must be treated as an input to the design flow and not merely a consequence of implementation.