According to some estimates, 73% of all system-on-a-chip design starts will contain mixed-signal content by 2006. Correspondingly, there’s a greater demand for mixed-signal functional verification that spans multiple design languages and is scalable when handling design abstraction.
Version 4.0 of Mentor Graphics’ ADVance MS (ADMS) functional verification platform now offers full language support for SystemVerilog, SystemC, VHDL, Verilog, Spice, VHDL-AMS, Verilog-AMS, and C. In addition, the ADMS platform is now integrated with Nassda’s HSIM hierarchical fast-Spice circuit simulator. The combination of ADMS and HSIM enhances designers’ simulation capabilities at the circuit level.
The ADMS platform’s range of language and abstraction support enables users to perform block-level validation and full-chip functional verification in one environment. That same environment extends both digital and analog verification to mixed-signal designs. It also enables digital-centric verification, such as testbenches with directed testing and pseudorandom testing.
On top of that, analog-centric verification is possible, including functions like circuit simulation (dc, ac, transient, parametric, Monte Carlo analysis, and corner-case analysis). Mixed-signal-centric verification comes in the form of checkerboard analysis for regression testing.
The tool integrates with Verisity’s SpecMan Elite to permit early verification of architectural or partitioning decisions. This verification can then be reused as a testbench throughout the design process.
Pricing for ADMS 4.0 starts at $110,000. It will be available in the second quarter of 2004 for Linux, HP, and Sun platforms.
Mentor Graphics Corp. www.mentor.com