Follow Heuristic Guidelines To Make Surface-Mount PC-Board Footprints

March 16, 2006
These rule-of-thumb specifications will keep your anxiety level low and your prototype design first-pass success level high.

Are you designing a pc-board (PCB) layout containing ICs or other components, but your PCB-layout software lacks footprints? Don't stress! Although it won't be optimized for production, you can quickly and easily create a PCB layout-package footprint that's suitable for prototyping.

Starting with only the data sheet's package-dimension mechanical drawing, the guidelines that follow will enable you to quickly generate the needed PCB apertures, such as top copper footprint, solder-mask-stop apertures, and solder-paste-stencil apertures. Normal caveats regarding optimization for production apply, but these guidelines will help you get your prototype designs into the lab for testing.

Some engineers lament that the days of "breadboard" prototyping are gone, along with the ability to quickly test and prove-out circuit ideas in the lab. Baby-boomer engineers fondly recall going from paper-napkin circuit sketches done in the evening to perfboard or wire-wrapped circuit prototypes built in the lab the next day, allowing them to verify operation and take waveforms to test out their concepts on the bench. (This did not mean, however, that they practiced willy-nilly wiring. Even before broadband, designers carefully considered component placement and reasoned out the routing of signal wires to prevent crosstalk, stray inductance, and stray capacitance from adversely affecting circuit operation). However, today's fine leadpitch small-outline integrated circuit (SOIC) and quad flat no-lead (QFN) package technologies are inherently unfriendly to hand soldering, and signal bandwidth is too high to be compatible with point-to-point "rat's nest" wiring. In addition, many semiconductor components—ASICs in particular—only come in surface-mount form. Therefore, prototyping with a dual-inline package before designing in an SOIC often isn't an option. Even if there are hand-solder-friendly packages, there may be differences in signal propagation and phase relationships between the prototype and the higher-density layout of a production design.

QUICK-TURN PCBs A PROTOTYPING PARADISE Sophisticated PCB CADlayout software has long since replaced the tedious, manual " tapeout" creation of PCB artwork wherein tape and adhesive-backed footprintpuppets were manually stuck down to mylar sheets in a 2 or 4 enlarged layout (for later photographic reduction and to create the 1:1 contact exposure film).

Now, engineers can automate the trial-and-error process of routing traces. The latest CAD software offers intuitive graphical user interfaces, plus it supports importing component and wiring information (that is, netlist information) from associated schematic-drawing (schematic-capture) programs.

These schematic-capture/PCB-layout software packages—when combined with an Internet-based, quick-turn PCB prototype house—can bring back the rapid breadboarding capability of yesteryear and still yield a prototype that closely resembles the final design. There are a number of software packages to choose from that cost less than a business lunch and take only a few hours to learn. Many include libraries of thousandsof common parts, eliminating the need to physically pick parts from bins and stuff them into perfboard.

The CAD-enabled path to a prototype is quick and easy with these five steps:

  • Start by drawing the circuit using the schematic capture software, picking components from the included libraries and connecting the wires and buses.
  • Import the captured circuit schematic to the PCB-layout software and move the component packages around for the least-tangled rat's nest. Then route the wires and have the software generate the CAM files.
  • Order the boards and solder stencil online. Upload the CAM files.
  • Once you have received the boards, you can start stenciling.
  • Assemble the prototypes.

Because the assembly step is expeditedby having the PCB, it more than makes up for any additional time required up front capturing the schematic and laying out the circuit. In fact, by using a solder stencil to screenprint the solder paste onto the PCBs, assembly becomes a simple matter of placing the components on the corresponding footprints and placing the board in a reflow oven. (Note: a dedicated "toaster oven" is adequate to the reflow task.)

PROBLEMS IN PROTOTYPING PARADISE? You may find that some of the parts required by your design don't exist in the software's library, but this is really quite common. (ASICs and new or unique devices may not be found in a PCB layout program's libraries of popular components.) In such a situation, the circuit-designer/would-beprototyper must create the device within the software package's libraries.

This includes not only the PCB copper footprint, but also the artwork for the solder stencil, solder masking, silkscreen legend, and component placement and orientation. However, a typical double-sided board will contain several unique layers associated with each component. There's no need for alarm, though. The task of creating the devices missing from the library isn't daunting if approached step-by-step.

COMMON REQUIREMENTS FOR TW0-LAYER BOARDS Start by defining the layers of a PCB component footprint. On the top of the board ("component side"), the requisite artwork layers are top copper, top solder-mask stop, top solder stencil, and top silkscreen legend. Common optional top layers may include component centroid/origin and documentation layers.

The top copper layer is, of course, the essential layer that establishes the copper areas where the device's solder connections are made. The top solder-maskstop layer's artwork prevents the liquid photo-imageable (LPI) solder-mask lacquer from covering the areas to be soldered. The top stencil layer (top cream layer) provides the aperture pattern for the openings in the thin stainless-steel stencil that "prints" the solder paste onto the associated area of the top copper layer. The silkscreen legend layer contains the artwork for the component outline and orientation, device ID, and part number.

The origin (part centroid layer) provides information to be used by pick'n'place equipment, and the documentation layer is commonly used to give a top view of the device. Neither layer appears on the physical board.

The data sheet for a device may or may not contain a drawing of a recommended footprint for the device's package. (If it does, then you would simply recreate the pad dimensions and pattern in the top copper layer.) But this information may be found in publications other than the device data sheet. Freescale Application Note AN2409, for example, provides footprintdimension data for whole families of fine-pitch SOIC packages.

We'll assume that a footprint drawing isn't supplied as we go through the step-by-step process of creating a surface-mount PCB footprint in a PCB-layout software program. For this exercise, we'll use the example of a power quad-sided flat no-lead (PQFN) package.

This advanced ASIC power package is defined in Freescale Application Note AN2467 as: "The PQFN is a surface mount plastic package with lead pads located on the bottom surface of the package. All PQFN packages have either been designed with a single exposed die pad (flag) or multiple exposed die pads, depending on device requirements and intended application. The industry standardization committee, JEDEC, has given a registered designator of MO-251 to describe the family of single exposed pad PQFN packages." The particular device data sheet we'll use in this example is the MC33922/MC34922 dual 4.0-A power H-Bridge.

Top Copper: To prepare the footprint, open the PCB-layout program's library editor and create either a new part in an existing library or a new library for the new part. Then select the menu option creating a new package. At this point, most PCB-layout software packages will present a 2D, layered drawing screen.

Now turn your attention to page 19 of the data sheet for the packagedimension drawing for the 29-Terminal PQFN plastic package, Case #1469-02 (Fig. 1). Note the dimension units, and set the grid on your drawing screen to the same units (millimeters in this case). Also note the dimensions of the package outline (10 by 10 mm). For reference, draw this outline around the drawing origin, using a temporary line that you will later delete.

The next step is to obtain the dimensions of the portion of the terminals (leads) that will sit in intimate contact with the PCB, since you'll need these to determine the size of the corresponding top copper pads. In this case, there are four terminal sizes: 16 terminals are 1.525 mm (nominal) long by 0.565 mm (nominal) wide; eight terminals are 0.775 mm (nominal) long by 0.565 mm (nominal) wide; four terminals are 1.005 mm (nominal) long by 0.565 mm (nominal) wide; and one terminal (the exposed heatsink pad) is a huge 9.4 mm (nominal) by 6 mm ( nominal) with approximately 1-mm radius bites taken out of each corner.

Finally, note the pin-center-to-pincenter spacing around the part's periphery— nominally 0.8 mm on centers. You now the basic dimension data needed to drawing the package footprint.

Now, for the first guidelines:

Guideline 1: For closely spaced, finepitch terminals, create the pad size width slightly less wide (say, 0.05 mm) than the lead/terminal width, and extend it outward about 0.15 mm longer than the lead/terminal length.

This helps preserve a minimum solder mask between the terminals and provides an externally visible solder fillet at the end of the terminals. The pad widths can be made wider for the production design. For prototyping, though, you want to make sure the risk of solderbridging between terminals is minimized so you don't waste time troubleshooting shorts caused by excess solder (a likely scenario with the hand-stencil-applied solder-paste process).

For the 16 1.525- by 0.565-mm terminals, this guideline equates to a PCB pad size of 1.675 by 0.515 mm. Thus, create this pad size in your PCB-layout software (for example, by selecting "change," then "Smd," and typing in 1.675 x 0.515). Do the same for each unique pad dimension (except the large heatsink pad; we'll get to that later).

Guideline 2: Create the footprint as it would be viewed looking down at the top copper of the PCB.

This means the pin 1 location and direction of counting will be as if you were looking down through the top of the part with X-ray vision. Many PCBlayout programs automatically number the pads in the order in which they're created on the drawing. Make sure to place the first pad in the pin 1 location, and increment in the direction of pin numbering as viewed from the top of the package.

To place these pads, you need to temporarily change your snap-to-grid spacing so that it equals one-half the nominal pin-center-to-pin-center spacing (in this case, 0.4 mm). Arrange the pads so that they're oriented identically like the terminals on the package. Remember to position them such that the length extends beyond the package perimeter by an additional 0.15 mm. Continue placing the pads going around the perimeter in pin-number order, remembering to change pad sizes when required, and re-orienting the pintopin baseline space when continuing onto adjacent sides (Fig. 2).

Guideline 3: Treat an exposed heatsinking pad (if required) as a separate and unique terminal pad having the ultimate number in the terminal sequence. Create the pad with slightly smaller dimensions (say, 0.1 mm in length and width) than the corresponding area of the package's exposed heatsink flag.

Specialized SOIC and QFN power packages have an exposed heatsinking flag that allows for the direct flow of heat from the bottom of the IC die to the PCB. For this to be effective, the PCB must have a corresponding exposed pad area with through-hole vias to sink the heat to a larger plane of copper (either on the bottom of the PCB and/or in interior layers of a multilayer PCB). Being an irregular shape, the exposed pad will need to be created as a polygon.

Take care to choose a line width narrow enough to produce the detail, but not so narrow that the figure eats up large amounts of CAM tool-processing time. (Remember, the polygon will be filled by drawing-in the interior using lines the same width as used to draw the polygon itself.) Some liberties may be taken to simplify small, complex features of the exposed pad, and care must be taken to maintain a minimum clearance with the perimeter pads of at least 0.2 mm (Fig. 3).

Before you continue, don't forget to delete the temporary reference line from the top copper. Designing the top copper for this pad isn't difficult, but the design of the corresponding solder-mask-stop layer and solder stencil layer for the exposed pad is somewhat tricky.

Top Solder-Mask Stop: After completing the top copper layer, the next logical step is to create the top solder-mask-stop layer's artwork. The solder mask covers the areas of the board where you don't want solder to adhere. Therefore, the soldermask stop comprises the apertures within the solder mask where the copper will be exposed for soldering.

There are two scenarios for the relationship between the copper pads and the solder-mask stop: The mask-stop aperture may be less than or equal to the corresponding copper pad's dimensions, or the mask stop may be greater than those dimensions.

In the first scenario, the pad is considered to be solder-mask-defined (SMD). That means the mask defines the solderable area of copper, since it overlaps it. This is advantageous in prototyping because it creates a trace that's doubly affixed to the PCB substrate and is therefore less likely to delaminate under the abuses of multiple desoldering and resoldering. It also supplies added protection against solder bridging and other shorts in the prototype.

In production designs, though, SMD pads for small terminals are undesirable. This is because the solder-mask edge on top of the copper pad creates a stress point in the solder joint that may crack when subjected to long-term temperature cycling. For this reason, in the production design, the stop-mask apertures should be larger than the pad dimensions to produce an open periphery of about 0.065 mm around the copper pad. This scenario is called non-solder-mask-defined pads (NSMD).

Guideline 4: Use SMD pads for finepitch leads when prototyping, and change them to NSMD pads when going to production.

In this PCB prototyping example, the SMD technique should be used. The easiest way to do this is to set the soldermask-stop apertures equal to the copper pad dimensions. If the PCB-layout software you're using automatically generates the stop masks, set its maximum size limit equal to the pad itself (that is, no growth in dimensions). It's also easy to create copper rectangles slightly smaller than the pads by zooming in and setting the resolution to finest. Then, draw the apertures on the top-stop layer while viewing and tracing inside the outline of the top-copper pads.

Once you've created the different pad rectangles, simply copy and paste them inside the pads. The large exposed pad polygon can be copied/cut and pasted as a whole entity into the top-stop layer. Figure 4 shows a zoomed-in view of one of the corners of the footprint with the top-copper and top-stop layers active in the PCB-layout software. Note that the rectangular pad has a top-stop opening (shown as yellow) that's slightly smaller than the pad (shown as gray), making this a solder-mask-defined pad.

Solder Stencil: The next step is to create the artwork that defines the solder-stencil layer. This stencil is used in a screenprinting process to precisely apply the solder paste to the pads on the PCB. The stencil is placed in intimate contact with the PCB surface; the pattern of holes should perfectly align with the pattern of copper. Then a rigid squeegee is used to force the solder paste through the stencil and onto the PCB. Even in a completely manual process, several boards per minute can be "printed" with solder paste, readying the boards for component placement.

Two factors determine the amount of solder paste applied to an area on the board—the area of the openings in the stencil, and the thickness of the stencil. Laser-cut, stainless-steel stencils for a prototype PCB can be obtained at the same time as the PCB. They're also available via Internet-based companies. A common thickness for such stencils is 6 mils (0.006 in.), which is sufficiently rugged to withstand indefinite use in a manual process. We'll assume this thickness as you design your stencil artwork layer.

Guideline 5: Use a 1:1 ratio for solderstencil openings for all pins/terminal pads, except any exposed heatsink pads or other large apertures. For large apertures (3 by 3 mm and greater), shrink the periphery of the aperture by 0.25 mm to allow sufficient clearance between the large pad and surrounding pin/terminal pads, and break the large pad's aperture into multiple "window panes."

For the terminal pads, the task is automatically accomplished if the PCB-layout software is reset from the "cream" option to "on" for the terminal pads that were created. This creates a 1:1 aperture for each terminal pad's stencil layer—a value that works very well for both fine-pitch and standard-pitch leads when using a 6-mil thick stencil.

For the exposed pad polygon, however, you will need to create the pattern manually. Start by turning on both the top-copper layer (so you can see the polygon) and the stencil layer, where you will draw the corresponding aperture. Next, choose the rectangle function in your PCB-layout software, and create a set of window-pane apertures within the area of the polygon. (Make sure that you're placing these rectangles on the stencil layer.) Figure 5 shows the finished stencil openings for the package overlaid on the top-copper pattern.

Note how the exposed pad stencil openings are pulled away (inward) from the perimeter of the polygon, and especially from the corners. This reduces the likelihood of excess solder and resulting solder shorts.

Top Silkscreen: The top silkscreen carries the human-interface information you wish to appear on top of the PCB. This silkscreen doesn't serve any circuit function, but it is important to prototyping. It will help orient and place components during board assembly and assist in testing and debugging the prototype.

Conventionally, the silkscreen consists of the component-name layer, place layer, and value layer. The component-name layer supplies the IDs for the part on the board—for example, U1, R1, C5, and Q2. The value layer would include any associated values for the component— for example, 1k or 0.01 F. And, the place layer contains an outline and orientation for the component. We'll consider the top-place layer as the minimum requirement for the device.

Guideline 6: Use minimum 7-mil (0.007-in.) line widths for silkscreen features. Change the font type to "vector" and adjust the ratio and size as required to create readable letters and numbers.

Don't be tempted to place numbers by every pin, but do label pin 1 on SOICs. On QFN packages, it's helpful to have the silkscreen note the corner "pin" numbers. Make the top-stop layer visible while drawing on the topplace layer. Be careful not to place the silkscreen numbers/letters/lines too close to the solder-mask-stop apertures. Otherwise, the ink will bleed over into the associated depressions in the solder mask on the finished PCB.

Adjust the font's ratio and size to achieve the most readable text while maintaining the minimum line width. It's also helpful to place an outline around the part perimeter. Figure 6 shows the minimum silkscreen content for the example device, with the soldermask-stop layer shown for reference.

By closely following these steps, you can create any PCB layout package footprint you need. The result is a PCB footprint that, while not optimized for production, is robust for prototype PCB applications. In particular, the achievable goal is to substitute schematic-capture software for "napkin sketches" and quick-turn PCBs with solder stencils in place of hand-wired breadboards, while maintaining a rapid concept-to-labwork cycle that supports the engineer's creative process.


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