Graphics DRAM Zooms At 6.4-Gbyte/s Aggregate Throughput

June 25, 2003
A throughput of 1.6 Gbits/s per data pin highlights the GDDR3 graphics DRAM. It represents an extension to the second-generation double-data-rate SDRAM technology. Developed by Micron Technology Inc., the GDDR3 homes in on high-performance graphics...

A throughput of 1.6 Gbits/s per data pin highlights the GDDR3 graphics DRAM. It represents an extension to the second-generation double-data-rate SDRAM technology. Developed by Micron Technology Inc., the GDDR3 homes in on high-performance graphics subsystems that use point-to-point connections between the graphics controller and the memories. Other applications involve high-bandwidth networking systems.

Organized as 8 Mwords by 32 bits, the 256-Mbit memory delivers an aggregate throughput of 6.4 Gbytes/s, which makes it the fastest high-density memory available today. It operates at rates about 50% faster than other memories used by graphics controllers at about half the power (approximately 2 W/chip) versus DDR2 SDRAMs. This reduces the overall power consumption of a graphics card. The GDDR3 memory bus includes on-chip 1.8-V termination, and both the bus and core of the chip operate from a 1.8-V supply.

The memory features single-ended Read and Write strobes and per-byte read-data and write-data strobe signals. A single resistor can be used to set the programmable impedance of the output driver, optimizing the interface to the graphics controller.

Available in a 12- by 13-mm 135-ball BGA package, the GDDR3 uses a single pin to control the pinout to provide both the standard pinout and a mirrored version of the pinout. Therefore, two chips can be mounted clamshell style, one on each side of a pc-board, without complex routing of the data signals.

Micron Technology Inc.
www.micron.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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