EDA> Design & Verification

Jan. 12, 2004
It's All Abstract For Verification

Megagate SoC designs require a different verification strategy than designs of yore. Designs with a well planned verification methodology will get to market first. With die sizes increasing and the migration to 90-nm design rules under way, design and verification complexity is outpacing existing methodologies.

Managing verification complexity demands levels of abstraction higher than the register-transfer level (RTL). Automated verification processes are mandatory for the lower levels of abstraction. There also is a pressing need for statistical Spice analysis for design yields. This less deterministic form of verification allows for "fuzzy" variations in process, operating environment, and operating life of the end product.

Today's SoCs carry a vast amount of densely packed interconnects combined with smaller VDD supply rails. The result is more nets with noise problems. This calls for analog analysis of the impact on digital behavior, in turn requiring a combination of static and dynamic methods to unravel.

In addition to tackling verification at higher levels of abstraction, such as timed and untimed transactional models, designers will begin moving toward partitioned verification. The divide-and-conquer approach is a practical means of achieving automatic verification at the transistor level. Divide-and-conquer is enforced because the EDA world still has separate verification engines for digital and analog designers. When it comes to the power-analysis side in particular, verification tools for 90- and 65-nm processes must be able to analyze both digital HDL and analog transistor-level blocks using a combination of static and dynamic methods.

RTL design handoff continues to gain ground, replacing gate-level handoff for ASIC, customer-owned tooling (COT), and structured ASIC implementations. Front-end design planning and RTL virtual prototyping have become firmly entrenched in many system houses' design methodologies. Such flows enable designers to find and fix downstream problems before lengthy and costly synthesis and place-and-route iterations.

SoC design methodologies are moving to a platform-based, application-specific form, requiring EDA tools that incorporate application-specific design expertise. Such trends will be particularly relevant to analog and RF design because a lack of experienced designers will be quickly exposed if tools can't apply some intelligence of their own.

  • SERDES SERIAL INTERFACES are becoming pervasive in high-end pc-board designs, bringing new design challenges. It's more important than ever for IC vendors to provide design kits. We'll see greater emphasis on design kits in 2004, not only for serializer/deserializer (SERDES) technology, but also for many high-speed interfaces.
  • WITH NANOMETER DESIGNS at high radio frequencies, designers will require verification at the transistor level to quantify ultra-deep-submicron analog behavior. There's an increasing need for full-chip, transistor-level simulation.
  • MIXED-LEVEL VERIFICATION is required for functional and, especially, post-layout verification of combinations of digital, mixed-signal, analog, RF, memory, and high-speed I/Os. Fortunately, hierarchical extraction engines are beginning to appear in the market, and they'll team with emerging full-chip transistor-level simulation tools.
  • ASSERTION-BASED VERIFICATION will become a mainstream verification methodology this year. Standardization of assertion languages, such as PSL and SystemVerilog, will provide the critical mass for a wider adoption of assertions by the design community.
  • AS ANALOG CONTENT RISES in complex SoCs, analog functions will need to be delivered in flexible form. Analog IP must be customizable to different specifications and portable to different processes. Hard analog IP blocks won't be up to the task and will begin to fall by the wayside. Designers will instead embrace soft analog IP that's much more reusable and more readily tailored to specific custom circuit requirements.
  • THE TREND IS TOWARD RTL ANALYSIS of designs, where changes are easier and much less costly. With average chip size increasing, engineering teams must find ways to analyze and debug chip designs earlier in the process. RTL design and analysis software is faster, more economical, and easier to adopt because it's considered a "pre-planning" tool that fits into an existing design flow.
  • THERE MUST BE REAL IP and testbench reuse to manage the level of SoC complexity found at the 90-nm process node. Process technology is driving a level of reuse demand that will take off in 2004. Extremely large functional IP blocks must have physical and verification attributes that make them easier to drop in and verify as they're employed in an SoC. Emerging verification tools coupled with high-level languages are supporting this reuse methodology.
  • LIMITED POWER CONSUMPTION will drive SoCs away from the focus on a single, very high-performance processor and toward the proliferation of software-processing engines throughout the design. We'll see more use of application-specific coprocessing engines with specialized architectures and instruction sets.
  • STANDARDIZATION WILL MAKE NEWS in 2004, with IP standards in the forefront. Organizations such as the Virtual Silicon Initiative Alliance are driving initiatives that will lead to improved IP quality, easier reuse of functional verification testbenches, greater design productivity, abatement of signal-integrity problems, and tighter IP protection.
  • DATA RATES OF UP TO 10 GBITS/S and third-generation I/O (3GIO) serial asynchronous bus architectures are replacing traditional high-speed pc-board design challenges (i.e., delay, timing, crosstalk, and overshoot) with challenges like jitter, lossy lines, and bit-error rates. From a pc-board design perspective, most of today's high-speed design tools lack the advanced modeling and verification requirements used by 3GIO technology. With the onset of serial asynchronous architectures, more pc-board tools will accept new design concepts for the routing of highly constrained differential pairs.

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