Board space is one reason. In some applications, semiconductor advances have pushed functional integration to such a high level that the IC and component packaging represents the real barrier to further miniaturization. One response has been to reduce the size of the IC packaging footprint to nearly the size of the chip—chip-scale packaging.
For passives, which account for a majority of the components in wireless handsets, discrete-device packaging is now miniscule. Just look at the 0201 and 0402 case sizes. And many efforts have been made to integrate passives, sometimes within ball-grid array (BGA)-style packages, and at other times using low-temperature cofired ceramics (LTCC) and thick film, or via thin-film-on-glass techniques. Embedding of passives within organic laminate structures also looks promising for the integration of passive components.
Connectors face similar demands for miniaturization, which is forcing manufacturers to develop connector and cable assemblies with higher I/O densities. For signal connectors, these demands are often complicated by requirements for gigahertz speeds, high reliability, and low cost. Power connectors must achieve higher I/O density by increasing the currents that can be carried per pin without exceeding temperature rise limits.
Moreover, performance motivates much of the packaging and interconnect R&D. Higher clock frequencies have made parasitics an issue for device and board-level interconnects. Many of the techniques used to reduce semiconductor package footprints also are motivated by the desire to shorten interconnects. These concerns affect interconnects at the chip, board, and system level, so they dictate requirements for chip-level packaging, IC sockets, board-to-board connectors, cable assemblies, and all other interconnects.
Similar concerns are driving the integration of power conversion components, such as dc-dc controllers and MOSFETs, to reduce the power losses associated with device interconnects. Another reason to focus on packaging is heat dissipation.
To get more power out of the power semiconductors, component developers are looking at packages that allow space for larger die, while reducing the thermal resistance from chip to board or chip to heatsink. On the control side, new multiphase topologies let power-supply designers better deal with thermal management, while reducing the need for external capacitors, which can occupy a good deal of board space.
Of course, thermal management is an issue for fast processors. There's an ongoing effort to push more air across these chips, which create smaller but hotter hot spots on the board. Additionally, attempts to cool the processor aren't being done in isolation.
The processor's cooling needs must be considered in light of the cooling requirements of other board and system-level components. The same concept applies to power supplies. You will, therefore, increasingly find power-supply builders delving into system-level enclosure design, and enclosure designers becoming more involved with power-supply design.
That level of attention paid to system- or application-level packaging is a concern for every chip, component, and module manufacturer. More and more, they must ask themselves, "What form of packaging makes my part more valuable in this application?"
Sometimes the answer is about size reduction. Other times it means increasing a device's performance to make other packaging issues easier. But in packaging, as in other aspects of electronic design, the device's value depends solely on its intended use. To paraphrase the old saw of retailing, the application is king.
Power connectors intended for use in modular power supplies will evolve to allow higher current per contact, more blind-mating options, and greater configurability. For example, designers will be able to configure their connectors to include a mix of power and signal pins with different pitches.
Faster speed signalling will call for greater integration of filtering components within connectors. For example, Molex expects to introduce a high-speed serial I/O device similar to the RJ45, but with integrated passives for balancing and filtering.
Multisource agreement groups rather than official standards groups will shape connector development. Because the standards process is often too lengthy, connector suppliers are working less formally with their customers to quickly hammer out de facto standards for interconnects.
Getting to 10 Gbits/s on the backplane will mean changes to the backplane rather than the connector. The obstacle is not the connector, but rather the traces on the backplane and the resistance they introduce. That resistance will be countered with wider traces and pre-emphasis or equalization. In some applications, the board material itself is changing as backplane developers adopt non-FR4 materials better suited to high speed signaling.
In servers, the move from bus-based I/O to switched-fabric-based I/O, such as InfiniBand, will spur development of connectors for these protocols. For example, the SpeedPAK I/O, adopted by InfiniBand to handle backplane connectors for up to 5 Gbits/s, replaces the PCI connector. Among high-end servers, there also is a trend to move I/O out of the server box, making it part of an independent rack-mount unit with 10-Gbit Ethernet ports.
Board-level interconnects will advance as designers seek greater bandwidth in backplanes and connectors. Conventional stamped and formed connectors should accommodate performance of up to 10 Gbits/s. But beyond this level, conventional stamped and formed connectors are reaching their limits in terms of density. So, connector developers such as Tyco Electronics (www.tycoelectronics.com) will be examining nonconventional methods like metallized particle interconnection (MPI) and pc-board technology.
Expect to see finer pitch and lower heights on board-to-board connectors. Pitches should dip below 0.3 mm, while spacing between boards is reduced to less than 2 mm.
MicroPGA (pin-grid array) packages and sockets will be dominant for Intel-style microprocessors in the coming year, reflecting the need for higher pin counts and tighter pin pitches. Microprocessor packaging has already begun to migrate from the PGA socket, with its 0.100-in. interstitial centerline spacings and through-hole assembly, to the MicroPGA package, with its 0.050-in. spacings and surface-mount assembly.
However, land-grid array (LGA) packages and sockets will continue to make inroads in RISC-based systems. The LGA relies on compression technology to achieve 0.050-in. centerline spacings and 1000- to 5000-pin counts. Ultimately, the LGA should become popular in desktop applications—perhaps in three to four years, after its cost drops.
Continued development of 3D packaging for vertical integration of components is on the way. In particular, the development of chip stacking will evolve to allow for new configurations of three or more stacked chips. The new variations will exploit both wirebonding and flip-chip attachment to connect the die to the substrate. Nevertheless, even more significant changes will occur as the technology should evolve beyond simple stacking of flash/SRAM to include more logic and memory combinations. Greater use of area array packaging will accommodate higher I/O devices. Variations on this theme, like package stacking, should also see further development. An example from DPAC Technologies (www.dense-pac.com), called CS-Stack, uses multiple transposer, interposer, and interface structures to stack two fine-pitch ball-grid-array (FPBGA) devices.
The emphasis in integration will shift noticeably from system-on-a-chip (SoC) to system-in-a-package (SiP), with cost and technical feasibility favoring the SiP approach. Development of organic laminate technologies with embedded components and microvias will help drive down SiP costs.
There already is activity in this area. Kyocera (www.kyocera.com) plans to go into production with high-density build-up organic packages for flip chips that promise to reduce flip-chip bump pitch to just 150 mm, and the use of laser-drilling to achieve through-via pitches of 220 mm in the substrate's core. Meanwhile, more established SiP techniques like LTCC and thin-film-on-glass will keep integrating larger functional blocks, particularly for RF applications.