Hoping to make its FPGAs attractive for wireless communications infrastructure applications, Xilinx Inc. has expanded its Xtreme DSP initiative with new algorithms and DSP development boards. Together, these forward error correction (FEC) algorithms and third-party DSP boards accelerate development of software-defined radio (SDR) for wireless communications.
A DSP processor core implemented in the Virtex II FPGA can perform SDR tasks with unmatched speed and flexibility, claims Per Holmberg, senior marketing manager for IP solutions at Xilinx. Using these new tools, he adds, designers can now create SDRs that are field upgradeable, allowing for cost-effective deployment of emerging wireless broadband standards.
The new FEC algorithms include a Viterbi decoder, a convolutional encoder, interleaving/de-interleaving, a Reed-Solomon encoder/decoder, and a 3GPP turbo encoder/decoder. These algorithms are critical for detecting and correcting errors in wired and wireless communication systems during transmission of data to optimize the use of available bandwidth.
Xilinx partners involved in developing these algorithms for the Virtex II series include Telecom Italia Lab, iCoding Technologies, and SysOnChip. Third parties involved in the development of DSP boards for SDR include Spectrum Signal Processing, Pentek, GV & Associates, Hunt Engineering, Nallatech, and LSP.
According to Xilinx, the additional forward error correction algorithms expand the Xtreme DSP offering to more than 70 cores, enabling designers to develop flexible SDR platforms on a single FPGA. Licensing details, instructions for downloading cores, and partner links can be found on the company's Web site at www.xilinx.com/ipcenter.
