ASIC Designers See Software's Potential

Several factors are blurring the line between ASICs and FPGAs. From design flows and performance to high-volume production rates, FPGAs are looking more and more like ASICs. This transformation is being helped by Altera Corp.'s recent introduction of the Quartus II Version 3.0 design software. Using this program, designers can develop a system-on-a-programmable-chip (SoPC) that blends the best parts of the FPGA and ASIC design processes. At the same time, this version promises to significantly reduce design and verification times for both FPGAs and ASIC-like mask-programmable devices.

Using this software, system designers can directly target HardCopy Stratix programmable devices. The advantages offered by the Stratix chip are twofold. On average, the company claims that the device is 50% faster than equivalent FPGAs. Secondly, it allows ASIC designers to directly design a mask-programmed version of Stratix. They can completely bypass the programmable-logic prototyping step.

In the past, users had to create a prototype version of their design with an Altera target device. If they wanted to create an ASIC-like, mask-programmable version, the users would then have to pass their design off to Altera's internal programmable-logic-device (PLD) design team. Because the PLD step is eliminated, users of Quartus II only need to hand off to the Altera team for placement and routing.

Keep in mind that the Stratix mask-programmed chips are part of Hardcopy. This program by Altera provides a path for converting FPGAs into ASICs. As part of this program, Altera is paid to remove the traditional FPGA excess routing in the conversion to the Stratix platform.

With this version of Quartus II, the company believes that users will still enjoy the advantages of prototyping their designs on FPGAs. Once all of the design issues have been addressed, a mask-programmable version of the design can be created using the Quartus II software (see figure). Altera estimates that HardCopy Stratix design cycles are typically eight months compared to 14 months for ASICs.

Several features and enhancements have been added to Quartus II Version 3. The principal improvement allows I/O assignment and validation to be performed during the design phase rather than after the chip has been programmed. Printed-circuit-board (PCB) layouts can then begin earlier in the design process.

In addition, two major improvements aid in reducing compilation time. The Chip Editor allows users to make small changes directly to an optimized design. It removes the need to recompile and repeat the timing analysis for the entire design. Instead, the Chip Editor only recompiles the design areas that have been changed.

The second new feature limits logic-placement changes during placement and routing. The changes are reduced to those introduced by incremental changes to any design source file. The placement and timing of the remaining design portions remain unaffected.

In the area of system-level design (SLD), the Quartus II design software offers SOPC Builder. This tool automates the addition, parameterization, and linking of intellectual-property (IP) cores. These cores include embedded processors, co-processors, peripherals, memories, and user-defined logic. This Quartus II release also includes the first SOPC Builder with support for the Red Hat Linux operating system.

The company's LogicLock feature also has been enhanced. With this application, users can lock down design blocks that are either timing critical or known to be good. They can lock down those blocks as early as placement.

The automation of the Quartus II software has been upgraded with a command line and Tool Command Language (Tcl) Scripting Interface. Tcl is a popular interpreted scripting language. Designers can use this interface to run Quartus from software or make files or Tcl scripts using a new, simplified programming syntax.

The design-optimization process also fares well in this new release. Design Space Explorer increases design performance by automatically applying combinations of compiler-optimization settings. Altera has reported a corresponding 20% increase in design performance over previous versions of Quartus.

Behavioral and timing simulations are now available via Model Technology, Inc.'s ModelSim software. This program is part of Altera's software subscription. The Quartus II Version 3.0 design software is available now for $2000 per node-locked PC license.