Prototyping Takes Center Stage

Prototyping is a well-understood practice these days, especially in the wireless arena. Using multi-FPGA pre-silicon prototypes (PSPs), wireless engineers can simulate a system-on-a-chip (SoC) device at near-real-world speeds and under real-world conditions—even in the presence of dynamically changing variables. Consider, for example, a cell-phone developer looking to try out his or her new design in the field. It would be incredibly difficult to model such real-world variables in software. The designer therefore creates a cell-phone prototype and drives it around to various select locations. He or she then makes calls on the cell phone and gauges its performance in real time.

While the concept of prototyping is well understood and utilized, it does not come without its difficulties. Failing to choose the right target for the PSP, for example, can have dire consequences in terms of cost, speed, form factor, reconfigurability, time-to-market, and overall project complexity. In recognition of this challenge, Aptix Corp. is now coming to market with a solution that promises to radically change how engineers think about and use pre-silicon prototypes. Known as the Aptix Prototype Studio, this family of software tools offers engineers a complete register-transfer-level- (RTL-) to-PSP flow. It also is hardware-target independent. In fact, the tool can target reconfigurable hardware prototypes as well as hardwired ones.

The Aptix Prototype Studio product family brings together a set of tools for engineers who no longer want to be constrained by a RTL-to-proprietary-hardware platform flow. It offers an open prototyping technology for engineers who want to utilize different target platforms. In some situations, for example, an engineer may opt for a target that consists of a hardwired board populated with FPGAs. Such a solution offers an excellent form factor. Plus, it is cost-effective in large quantities and can run fast. Other engineers, however, might want the option of choosing an FPGA-based prototype with a reconfigurable interconnect and better debugging capabilities. But they're leery of the associated cost. Because the Aptix Prototype Studio product family and the Aptix reconfigurable hardware products are being offered with term pricing, cost is no longer a limiting factor in choosing the FPGA-based prototype.

Either way, Aptix Prototype Studio is target-independent. Users are therefore free to utilize the hardware target that they deem most appropriate. In the meantime, it provides them with the software needed to create a pre-silicon prototype. A third-party vendor can utilize this flow to create hardware. Or the user can produce the hardware him- or herself. As an alternative, the user can utilize Aptix as a partner to access a reconfigurable solution.

The fully loaded product, Aptix Prototype Studio Enterprise, consists of five components: Design Pilot, Explorer, the Module Verification Platform (MVP), FPGA Connector, and SmaRT (see figure). FPGA Connector was developed by Translogic BV of Ede, The Netherlands. How exactly does the Prototype Studio software work? Starting with Design Pilot, the SoC structures that must be converted to FPGA structures are identified. Many are fixed automatically. Design Pilot then automatically partitions the design into multiple FPGAs, while encapsulating the user's chosen FPGA synthesis tool. Among the synthesis-tool options currently supported are Synplicity and Synopsys.

If and when pin optimization is required, additional pin management logic is inserted automatically. Throughout the process, correspondence is maintained with RTL signal names for later use in debugging. The output from Design Pilot is a set of netlists for the prototype FPGAs. At this point, the user must select the PSP target hardware.

The Module Verification Platform contained within Aptix Prototype Studio supports a block-based methodology. It maps a design from SoC RTL into FPGAs one block at a time. Using MVP, portions of a design can be run in the prototype and co-emulated with the rest of the design or a test bench running on a workstation. This aspect is especially useful during a design's architectural exploration stage, using tools like SystemC and SPW, and in confirming that a block is FPGA-ready.

Instead of a custom PCB, the user could select the PSP target to be the Aptix System Explorer or Software Integration Station. Aptix's Explorer software would then be used for the physical mapping steps. Explorer takes the netlists produced by Design Pilot and sends them to Xilinx place and route. The reconfigurable hardware is mapped and routed. Probes are inserted as specified by the user, and a bitstream is produced for loading the entire multi-FPGA prototype.

Though this process sounds deceivingly simple, a host of innovative features make Prototype Studio software noteworthy. For starters, the software provides a smooth transition between different hardware-prototyping platforms. This feature allows different verification teams (hardware, firmware, or software) to communicate design and debug data at the hardware level. It doesn't matter that each one is using different hardware prototypes for their verification efforts.

This communication is seamless. It is done via bitstreams of information that are sent back and forth between the various platforms. For example, suppose a software engineer is debugging the registers and finds a bug in the hardware. This information can be immediately communicated to the hardware engineer, who is working on a reconfigurable platform. The hardware engineer can fix the problem and send a bitstream of information back to the software engineer. The fix is embedded inside.

This capability is crucial, because the hardware/software interface is often one of the most difficult parts of the design process. Because the lines of communication are open, the hardware engineer is now able to make better choices that will not adversely affect the software and vice versa. Subsequently, the time that it takes to get both the hardware and software working can be drastically reduced.

Another notable feature of Aptix Prototype Studio is its ability to identify different coding styles in the SoC netlist. When the tool detects a style that is not friendly to FPGAs, it automatically converts the netlist into a more workable style. Expert users can accomplish the same task using a built-in Tcl scripting capability.

Partitioning is another key feature of the Prototype Studio software. To increase productivity, the tool provides three modes of operation for this task: fully automatic, fully interactive, and a hybrid version of the two. Partitioning the design among a set of FPGAs without adequate tools can be a tedious, time-consuming, and error-prone process.

In addition, a pin-management capability ensures that the mapping of pins from the SoC to the FPGA goes smoothly. While the pin number is not an issue for the SoC, an FPGA has only around 1100 pins. The engineer can easily find him- or herself in a sticky situation. Because pin mismanagement ultimately affects the partitioning, this is one problem that must be addressed directly.

The Aptix Prototype Studio product family is available in four different configurations. Aptix Prototype Studio/Pro contains Design Pilot, Explorer, and the MVP. It targets the Aptix reconfigurable platforms. Aptix Prototype Studio/PCB comes with Design Pilot and FPGA Connector. It supports custom hard-wired PCBs for FPGA-based SoC design. Both packages are available now. Pricing starts at $79,500 for a one-year license of Aptix Prototype Studio/PCB. The Aptix Prototype Studio/Enterprise version is a full-featured product containing Design Pilot, Explorer, the Module Verification Platform (MVP), FPGA Connector, and SmaRT. It can target all hardware options and is available now.

Aptix Prototype Studio/SmartPCB will not be available until next year. The SmartPCB product will contain Design Pilot, FPGA Connector, and SmaRT. SmaRT, the Aptix "smart" Run-time Tool, will come with Aptix intellectual property (IP) that can be used for populating target hardware. It will give hardwired pre-silicon prototypes the advanced debugging technology that was formerly reserved for reconfigurable platforms.