Platform Straddles Prototyping And Emulation

Launched some two years ago, Emulation and Verification Engineering's (EVE) debut product—the ZeBu-ZV prototyping system—was touted as a "personal emulator." It remains popular as a prototyping platform, offering the best features of emulator and FPGA-based prototyping platforms in one product.

But the ZeBu-ZV came up short in capacity. The board had two large FPGAs with capacity limited to 1.5M ASIC gates. That initial product, however, was seen from EVE's inception as the first in a projected family of prototyping systems.

Meanwhile, FPGA capacities, as well as system-on-a-chip (SoC) design sizes, have expanded. After about a year of development, larger FPGAs and SoC designs find their confluence in EVE's ZeBu-XL. The next-generation prototyping system has the capacity to handle very large SoC designs and offers a number of features that engender ease of use and flexibility in debugging.

Whereas a single ZeBu-ZV board's capacity totaled 1.5M ASIC gates, the ZeBu-XL delivers a 30-fold increase in capacity with up to 48M ASIC gates. In terms of performance, ZeBu-XL can run at up to 30 MHz in standalone or in-circuit emulation modes in its smallest configuration (Fig. 1). Large configurations of near-full capacity still run at 1 to 2 MHz, which is considerably more than can be achieved using hardware-assisted emulation systems.

That kind of capacity is craved in this age of SoCs with more than 5M ASIC gates. The speed, too, is critical to those looking for a truly usable prototype with which to verify hardware, software, and their integration.

The system is based on Xilinx's Virtex II 8000 FPGAs. Capacity can be incremented in multiples of two FPGAs up to 64 maximum. Memory is also modular and expandable up to 1.5 Gbytes.

A number of factors contribute to ZeBu-XL's speed. First, there's the size of its Virtex II 8000 FPGAs, which holds down the number of FPGAs required to map a design. Emulators can have hundreds, if not thousands, of FPGAs on multiple boards interconnected by backplanes. ZeBu-XL consists of just one motherboard and four modules. So routing complexity is greatly decreased, both by the larger FPGAs and by the system's overall smaller footprint. In addition, the system's low-power design allows fast 80-MHz clocks to be used for its double-data-rate (DDR) memories.

ZeBu-XL is integrated with the most popular ASIC and FPGA synthesis tools and includes a complete compilation software suite. The compiler provides a number of critical features that put ZeBu-XL ahead of many emulators in terms of functionality and ease of use. Among them are automatic gate-level partitioning, automated clock processing, and a memory generator.

A very important aspect of the system is the Reconfigurable Testbench (RTB). This technology, launched with the earlier ZeBu-ZV, comes enhanced in the new version with an eye toward automation. For instance, the RTB now offers improved handling of synchronous and asynchronous clocks thanks to a dedicated clock server. It also offers more memory and more flexible ways to implement memory access with multiport access.

Crucial to the RTB's utility is its ability to change test environments, say from a Verilog simulator to a C testbench, without the need to recompile the design itself. Only the RTB must be recompiled in such circumstances, which takes just minutes. Other emulators and prototyping systems would require recompilation of the design itself as well as the testbench, which takes hours.

How is this accomplished? In emulators, as in ZeBu, FPGAs become resources for mapping both the design and the testbench interface. But those resources are shared, which necessitates recompilation of both when test environments change. ZeBu is designed with separate resources for the RTB and the design under test (DUT). Different pools of FPGAs and memories for each exist on separate boards (Fig. 2). It's a clean approach that sidesteps potential DUT routing issues that can arise with full recompilation. Traffic between boards is handled by a set of four Virtex II 6000 FPGAs that compose a traffic hub.

As with the earlier ZeBu-ZV system, the ZeBu-XL offers various stimulation modes, including HDL co-simulation, C/C++ co-simulation at cycle or transaction levels, and pattern mode for regression testing, as well as standalone and in-circuit emulation. All of these modes can be simultaneously combined together for maximum flexibility and performance.

The original ZeBu-ZV supported in-circuit emulation only through the Smart ICE connection (limited to 16 I/O signals and 10-MHz maximum speed) and the IcePod (744 I/O signals and 800-MHz maximum speed). ZeBu-XL adds a Direct ICE connection, which supports about 1100 I/O signals and a maximum speed of 30 MHz.

The system supports hardware/software integration and embedded software validation. By connecting a software debugger to a CPU or DSP modeled either as a soft core mapped into the emulator or a logic tile/hard core mounted inside the system, ZeBu-XL functions at megahertz speeds.

ZeBu-XL offers multiple interactive hardware debugging features, including flexible software logic analysis. Users have access in their C/C++, SystemC, or HDL simulator to any I/O pins of the DUT and/or any register output of the DUT. Other debug features include continuous internal state capture; read and write to any memory of the DUT FPGAs and memory modules; register read and write to any of the DUT FPGAs; and save and restore.

Few emulators or prototyping systems support the save and restore feature. A user can run an emulation for billions of cycles, stop the emulation run, save the entire state of the machine, reload it, and restart the emulation from the point at which it stopped. Though commonly supported by simulators, this feature is rarely found in emulation. And when it is found, it's not used often because reloading the machine state can take hours. ZeBu-XL accomplishes this feat in a matter of seconds.

In addition, the system supplies a powerful built-in logic analyzer for fast hardware logic analysis on all I/O pins and static probes at up to 12 MHz. It can also perform on-the-fly monitoring using dynamic probes at full speed. Up to 8 Gbytes of captures into SDRAM are supported, as are 64 static and dynamic hardware triggers.

Starting price for a ZeBu-XL system is $120,000. A full 64-FPGA configuration with dynamic probing, logic analyzer, and all other bells and whistles tops out at $1.75 million. The system is available now.