Ethernet Processor Cuts Networking Overhead

Aug. 9, 2004
This multiprocessor chip uses hardware acceleration to handle remote DMA and iSCSI by itself.

Ethernet is everywhere. It's easy to use and install, but the advent of 1-Gbit/s Ethernet is stressing even the latest gigahertz processors. So, it's hardware acceleration to the rescue.

Heeding the call, Siliquent Technologies' Ethernet Processing Unit (EPU) takes Ethernet hardware acceleration a step further than TCP offload engines (TOEs) by handling a range of protocols. Its microprogrammed architecture allows future support for new protocols as well as system customization. Vendors looking for this level of customization will have to work with Siliquent.

The EPU targets processing clusters, network storage, and high-performance servers. A primary goal for the EPU design was to significantly reduce the host overhead for servicing network traffic. Another key to its design was the ability to handle multiple protocols simultaneously.

Performance tests show that the EPU can cut host loading by a factor of two to three when handling protocol processing for the host similar to TOE operation. The EPU can slash overhead by an additional factor of five or more with Direct Data Placement or remote DMA (RDMA) support. Both give the EPU direct access to host data. This means that the host processor needs only to be involved once data is available, instead of having to manage message tables and queues.

Siliquent's testing with a 1-Gbit/s link connected to a 1.4-GHz Opteron server running Linux shows a 70% processor utilization with a conventional network adapter versus 4% for the EPU. Without the EPU, even the fastest of today's processors couldn't hold their own at 10 Gbits/s.

The EPU comes in two versions. The SLQ1010 handles a single 10-Gbit/s Ethernet link (see the figure), while the SLQ1004 has four 1-Gbit/s links. Both support a 133-MHz, 64-bit PCI-X interface and operate at full line speeds. End-to-end latency at 10 Gbits/s is under 10 µs.

MULTIPLE PROTOCOLS The EPU handles TCP/IP, but its support for other protocols like iSCSI, iSER (iSCSI extension over RDMA), iWarp (RDMA over IP), NFS over RDMA, and SDP (sockets direct protocol) makes things interesting. These protocols let the EPU handle more of the processing for the host rather than simply transferring data and identifying the protocol in use.

The EPU has a small amount of flash memory for booting. It loads microcode into the EPU's on-chip memory, making for easy updates. Also, Siliquent provides open-source Linux drivers for the EPU. These provide interfaces to standard application programming interfaces such as NFS kDAPL and Oracle uDAPL. SCSI support can utilize iSCSI, iSER, and iWarp.

Pricing for the EPU chips will be approximately $200 per port. Price and performance are only part of the story, though. Power requirements were reduced as well. The SLQ1010 consumes 5.5 W, while the SLQ1004 runs at 4 W. Adapter boards will typically use less than 17 W. Low power is critical, especially for blade servers that utilize a pair of EPUs for redundancy. Dual star fabrics are becoming the norm for high-availability systems.

Ethernet has the benefit of being familiar, but 10-Gbit/s Ethernet is going to need support chips like the EPU to contend with the likes of InfiniBand. When it comes to efficiency and performance, InfiniBand may still have the edge. Nonetheless, Ethernet has won similar battles in the past—not by being the fastest or the best, but by being suitable and surviving.

Siliquent Technologies

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