Preconfigured Compute Optimized "Supercell" Reduces Time-To-Market

Oct. 13, 2005

Time-to-market drives many design decisions in the ASIC arena. By precombining and verifying a collection of key blocks of circuit intellectual property (IP), designers at Kawasaki Microelectronics America (K-Micro) hope to further accelerate the design

Dave Bursky

The Topaz computing subsystem is a large megacell (or supercell) based around the MIPS32 24Kf 32-bt RISC processor, which combines many of the popular CPU support functions ASIC designers typically would want to integrate as part of their chip design. Such a solution would fit well with applications like passive optical networks, set-top boxes, printers, routers, and storage devices.

The MIPS32 24Kf CPU operates at 200 or 400 MHz. It packs an integrated floating-point unit, 32-kbyte instruction and data caches, and a memory-management unit. An interrupt controller, a DMA controller, a serial interface, a memory controller for DRAM, and a second controller for flash memory surround the CPU. Licensed from SafeNet, the EIP94 encryption engine supports DES, 3DES, AES, and ARC4 encryption schemes and MD5 and SHA-1 hash engines. The supercell also includes a block of SRAM and many peripheral I/O functions to provide additional resources and further reduce the system-on-a-chip design time.

K-Micro used the Sonics Silicon Backplane III to integrate the blocks. This backplane provides a 128-bit wide, 200-MHz on-chip bus. The company also used the Sonics S3220 crossbar interconnect for lower-speed peripheral support blocks like timers, UART, GPIO lines, the watchdog timer, and the I²C port.

By using the Silicon Backplane, K-Micro makes it easy to connect additional custom or standard blocks to the backplane using the open-core protocol interface. As a result, designers can customize the Topaz subsystem if they want to add functions or remove functions not needed for their application.

Pre-integrating and verifying the operation of the Topaz "superblock" can considerably reduce the amount of time customers need to design and verify the full ASIC. This accelerates time-to-market and reduces development costs.

The initial implementation targets 0.13-µm processes. It's already siliconproven in TSMC's foundry. A development board with the core implemented in silicon and an FPGA prototyping card are available for system developers to validate and debug designs before moving to an ASIC (see the figure). Contact the company for licensing terms.

Kawasaki Microelectronics America Inc.
www.k-micro.us

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.