Chips Don't Float in Space! (But They're Often Designed In A Vacuum)

Dec. 4, 2006
The challenges mount for designers working feverishly on the latest chips, tackling power, density, signal integrity, and much more. What's often overlooked is the not-so-insignificant fact that chips don't float in space — they are assembled onto package

The challenges mount for designers working feverishly on the latest chips destined for the iPod, Blackberry, RAZR, or the next hot network chip set. These unlikely superheroes have tackled power, density, signal integrity, and much more. What's often overlooked is the not so insignificant fact that chips don't float in space — they're assembled onto packages and increasingly onto systems-in-packages (SiPs).

This disregard of the chip's environment needs to change... and change quickly. Consider this: Distributing clean power to a chip's core and I/O ring is vitally important for meeting a timing budget. Most power analysis is done using component models that aren't accurate enough to imitate the interaction between the chip and SiP, package, or pc board. Hidden geometry-dependent resonances combined with on-die parasitics within a SiP can starve the die of power. In a worst-case scenario, a die passes traditional component-based timing analysis but fails in the field due to power problems, which can then lead to lengthy system debug and — even worse — unhappy customers.

Moreover, the often mysterious and elusive practice of simulation-measurement correlation is only as good as the models used. This imprecision can cause an overly conservative design or introduce extra product risk, which adds bottom-line costs and loss of efficiencies.

SiPs and IC packages don't float in space, either. A common approach to SiP design is to stack packaged die, known as package-on-package (PoP) or package-in-package (PiP). A primary reason for this is the "Known Good Die" (KGD) problem caused by the inability to test a die completely before assembly, affecting the yield of the final SiP.

Of course, whether it's a PiP, a PoP, a bare-die SiP, or a package, the resulting component will be assembled onto a pc board and, at high enough frequencies, the different component boundaries don't necessarily equate to good electrical model boundaries. Not only do discontinuities, resonances, and current hot spots occur within individual components, but even more worrisome, these effects can occur as a result of complex component interactions, requiring an analysis of the unified system to reveal them. Signal and power waves travel through redistribution layers, wire bonds, solder bumps, power rings, solder balls, and vias with total disregard for the attempts to model these structures as independent entities.

The placement of decoupling capacitors, or decaps, is essential to guaranteeing circuit performance. Most system designers place decaps across a wide frequency spectrum, an extravagant and expensive endeavor. And, modeling the board, package, and die as separate structures with independent decap requirements is a drain on the budget. Designers can miss hot spots that occur from component interactions, place redundant and wasteful components in the system, or place components with incorrect values due to resonance movement from the system integration. When analyzing PiP, PoP, SiP, and pc boards, real estate for decaps is at a premium, and locating the optimum location and value requires a detailed model that considers all possible current return paths.

Moving forward, what's a project team to do? More and more, specialized electronic design automation (EDA) companies are developing software that straddles the line between a chip and its package or system. They can offer ways to model real-world boundary conditions, giving designers additional confidence in the correlation of simulation versus measurement, along with field reliability. They offer software that enables a common meshing approach across all interconnect fabrics for unified signal, power, and simultaneous-switching noise (SSN) model generation and a way to analyze the signal and power delivery system.

There's no question that the challenges affecting chip design are complex and only getting more so as small process geometries become available. What's often overlooked is the relationship the chip has with its package and the rest of the system, which is why it's important to remember that chips don't float in space and shouldn't be designed in a vacuum!

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