3D Methods Push The "Thin Is In" Craze

Jan. 11, 2007
More than three decades ago, Moore's Law predicted IC development would one day come to a halt, since the fundamental laws of physics would keep chips from shrinking any further. Though that prognostication hasn't come true yet, two surprising factors pr

More than three decades ago, Moore's Law predicted IC development would one day come to a halt, since the fundamental laws of physics would keep chips from shrinking any further. Though that prognostication hasn't come true yet, two surprising factors previously not considered are throwing up roadblocks to further breakthroughs—packaging and interconnects.

Both have been driving IC process, assembly, and form factor developments, enabling designers to scale down chip line geometries to the tiniest of dimensions. Still, formidable challenges lie ahead as ICs dwindle in size. Testing and packaging costs are rising. In fact, they can cost as much as the die the IC is made on, if not higher, representing a significant portion of the IC's overall cost.

Steps in IC design are merging within the product-development cycle. It's becoming more common to simultaneously craft an IC chip, its package, and the board it's mounted on. Of course, there are the power requirements for ICs designed with 90nm line widths and below. Thus, designers must also account for IR voltage drops in the package and include them in the overall design optimization. Then, add in the concomitant rising heat-dissipation levels for smaller chip and interconnect areas, which demands more sophisticated heatmanagement techniques. It all makes for a challenging task, indeed.

To increase packing densities, IC manufacturers are clamoring for advanced manufacturing and packaging techniques, such as wafer thinning, system-on-a-chip (SoC), chip and board stacking, system in package (SiP), chip-scale packaging (CSP), wafer-level chip-scale packaging (WLCSP), multichip packaging (MCP), and package on a package (PoP). All these 3D approaches strive for greater densities through the vertical Z axis.

PoP and WLP represent two of the hottest 3D packaging technologies. Until recently, WLP was limited to ICs with less than 20 pins. Using more pins tended to trigger reliability problems, caused by differences in the thermal coefficients of expansion between the silicon ICs and the pc boards on which they were mounted. New WLP technologies promise packaging of ICs with up to 100 pins.

Tessera Technologies has announced one of the thinnest WLCSP products, coming in at a mere 0.5 mm (Fig. 1). Aimed at companies developing advanced electronics with integrated cameras, it's built on Tessera's Shellcase technology's innovative packaging approach.

Many 3D packaging approaches are being pursued. Whether or not designers stack chips and die on top of each other or place them as separate die, interconnecting them in a single package can lead to different reliability and yield results. These varied results are largely influenced by the types of chips and dies involved, the complexity of interconnecting them, and the intended application.

Samsung Electronics Co. devised an ultra-thin (1.4 mm) 16-chip stack of NAND flash memory in an MCP (Fig. 2). Each wafer is thinned to 95% of its original thickness (as used in a previous-generation MCP) to produce an overall thickness of 30 mm. The company then trimmed an adhesive layer used between each chip and the next one from 60 to 20 mm.

Ziptronix's Direct Bond Interconnect (DBI) technology enables scalable, high-density, electrical interconnects bonded in a die-towafer scale method. DBI achieves the highest density of electrical connections for 3D ICs—4 million connections/cm2 (Fig. 3). It represents an advance of Ziptronix's ZiROC direct bond technology, which enables covalent, room-temperature bonds between the silicon-oxide surfaces of each chip in the 3D structure.

IMEC has pioneered many 3D packaging concepts for a number of wireless, medical, consumer, and other applications, including SiP, WLP, and a unique stacked-IC (SIC) concept (Fig. 4). In the SIC, small silicon vias with copper nails are used before the front-of-the-line process step.

The Heat Is On
As IC line drawings scale down further, thermal management and heat removal are becoming ever more challenging—not only for the chip itself, but also for the interconnects as they, too, shrink. Heat in particular is a problem for newer graphics and high-speed processors.

While heatsinks, fans, and blowers continue to advance, they'll no doubt lose effectiveness for future-generation ICs and packages. Even so, better heatsink and thermal interface materials are lending a helping hand. So are advanced thermal-management chips, liquid-cooling methods, and nanoengineered thin-film materials (see "Back to Cool School").

Cost, reliability, bulkiness, and quietness still plague modern liquid-cooling methods. According to Intel, the size and cost of liquid cooling is six times greater than air cooling. Asetek A/S claims to have narrowed that cost ratio to 1 to 1.5 times that of air cooling. Its proprietary IP liquid-cooling integrated pump, reservoir, and cold plate comes in one compact device that's smaller than a traditional heatsink.

IBM has found a way to double or even quadruple the amount of heat removed from a given area by employing presentday, air-cooled methods. Using liquid cooling and manifolds with high-thermal conductivity interfaces, IBM has achieved thermal power dissipation up to 24 W/in.2 from the present-day limits of 12 W/in.2 for air.

However, these developments are still at the lab. A void remains in the hardwareand software-tool departments, which leaves designers scrambling to get a better understanding of thermal management issues. The good news is that the design and packaging communities are on top of the situation, in pursuit of appropriate solutions.

For more, see "Integration Via Semiconductor Packaging."

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