Input Ripple-Current Balancing By Phase Shifting Multiple Outputs

May 2, 2012
When using multiple dc-dc converters to increase current capacity, don't just synchronize their clocks, phase-shift the clocks, too, to reduce stress on input capacitors.

Synchronizing the switching frequency of on-board converters is an increasingly popular way to control electromagnetic interference (EMI) and avoid beat frequencies. Unfortunately, frequency synchronization carries a penalty—added stress on input capacitors. Fortunately, there’s a simple solution—shifting the phase of the synchronization signal to each converter.

Before describing the solution, we need to understand the source of the problem. The current from the supply to the converter is mainly dc, but the converters’ input capacitors deliver a discontinuous pulsed current. So selecting the appropriate capacitor is a straightforward matter of designing for the desired ripple and RMS current.

But when there are multiple converters on a board, the designer can receive an unpleasant surprise. Any one converter is not going to sink current from just the capacitor designated on paper as its input capacitor. Certainly, most of the current will come from the nearest low-impedance source. However, every other low-impedance source on the board will contribute some portion of the needed current according to the parasitic impedances between that capacitor and the converter.

In a synchronized system, all the converter pulse currents are drawn simultaneously. As a result, the capacitors have to handle a larger RMS current. Significantly, the power dissipated in a capacitor’s equivalent series resistance (ESR) is proportional to the square of the RMS current. Thus, the capacitors are thermally stressed beyond expectations compared to the operation of only one converter. This reduces reliability and increases noise peaks in the conducted emissions profile.

Fortunately, phase shifting provides a simple solution. The clock edges are delayed so they arrive at different converters at different times within the clock period. This mitigates the overlap of pulse currents in the input capacitors, reducing their RMS current.

Phase-shifting the synchronization clock can be done with analog circuitry or FPGAs, but they increase component and development costs. Fortunately, there are several digital pulse-width modulation (PWM) controllers that integrate synchronization and phase shifting (Fig. 1).

1. The PowerXR System is a unique four-channel digital PWM controller that offers clock synchronization and phase shifting.

Demonstrating The Problem

Figure 2 proves that the charging inductor current is the sum of current sourced from all four clusters of input capacitors even though only one channel is operating. In this example, the conversion is 12 V to 1 V with an 11-A load. The waveforms show the current through the inductor plus the currents from all four clusters of input capacitors. The labeling is for capacitor current and inductor currents.

2. The charging Inductor current for one operating channel is the sum of the input capacitor currents across all four channels. This demonstrates the concern that more than one capacitor delivers the pulse current for a given output.

In Figure 2, phase shift isn’t used, so the current pulses I_L1 through I_L4 occur simultaneously. This produces a single large “burst” in I_Cin1. In Figure 1, phase shift has been applied to desynchronize the current pulses, resulting in four times as many bursts, of lower amplitude.

All Together, Now!

Now that we see the problem with just one converter, we can observe the impact on an input capacitor from multiple operating converters. The PowerXR controller was reconfigured as a typical high-power embedded design with the following outputs from a 12-V input:

Channel 1:  1.8 V at 3.5 A

Channel 2:  1.2 V at 9.4 A

Channel 3:  2.5 V at 4.9 A

Channel 4:  1.0 V at 11.4 A

Note that the peak current is nearly 5 A, and the RMS current is 1.26 A (Fig. 3). If the capacitor’s current supplied only channel 1, then it would peak at only about 1.6 A, with a much lower RMS current (assuming ~90% efficiency): 

3. The measurement of the input capacitor current sourced from Cin1 when all four channels are operating and not phase shifted demonstrates a higher than expected pulse current if phase shifting is not implemented due to all four channels sourcing current—not just one.

This is not what actually happens, and it requires the designer’s attention.

Figure 4 shows the same test conditions, with one change. The PowerXR controller is configured to put the switching stages 90° out of phase. This can be most clearly seen in the inductor current waveforms. Note how the current pulses through channel 1’s input capacitors are now at a higher frequency and of significantly lower amplitude. These changes reduce the capacitors’ RMS current to 885 mA. This is a 51% reduction in ESR dissipation, compared to 1.26 A when phase shifting isn’t used.

4. The measurement of the input capacitor current sourced from Cin1 when all four channels are operating and are also phase shifted demonstrates a lower RMS current on a given capacitor is achieved by phase shifting because each channel is sourcing current at a different time.


These results demonstrate that shifting the phase of the clock-synchronization signal significantly improves regulator performance.

  • Less heat is generated, so reliability is potentially increased.
  • EMI troubles are mitigated due to the reduced amplitude of the pulse currents at each stage as well as the increased effective frequency of the pulses
  • Less expensive (and possibly fewer) capacitors are needed.

Sponsored Recommendations


To join the conversation, and become an exclusive member of Electronic Design, create an account today!