Electronicdesign 1624 Xl ds

Control Jitter And Interference During Clock Distribution

Oct. 8, 2009
Several practical issues must be addressed when designing the clock tree for a system running synchronously at high speed. This Design Solution takes you through the basics of controlling jitter and interference stemming from clock distribution.

Several practical issues must be addressed when designing the clock tree for a system running synchronously at high speed. First is the signal integrity of the clock itself, i.e., maintaining low jitter and low distortion all the way to the receiver. Second is controlling clock interference with other parts of the system, as well as compliance with electromagnetic- interference (EMI) regulations.

These issues are easy to understand, but hard to practice without proper guidelines. Practical solutions are available, though, and many methods can be applied to any high-speed design.

MINIMIZE CLOCK SIGNAL DEGRADATION There are two major effects to consider when distributing a high-speed clock: trace attenuation and reflection.1 Even though the clock speed might not be high, its rising and falling edge needs to be sharp for low-jitter performance.

From a spectrum point of view, the edge consists of many highfrequency harmonics. The board trace material is lossy, acting like a low-pass filter. The amount of attenuation is more severe as the frequency goes higher and the trace gets longer.

When the signal arrives at the receiver, different frequency components are attenuated differently, distorting the edge and increasing jitter. This is trace attenuation. There’s little one can do to counter this issue, other than choose high-swing mode when attenuation dominates.

Reflection is a bigger problem for clock distribution. Figure 1 shows simulation results with an unterminated trace. The driver output impedance is at 25 Ω, and the characteristic impedance of the trace is 50 Ω. The receiver has high-input impedance.

The ideal signal is the green signal with 3.3-V swing at 45 MHz. The blue signal is the signal at the driver’s side, and the red signal is the signal at the receiver’s input. Maximum voltage at the trace end is approximately 4.4 V instead of 3.3 V, and the minimum voltage is approximately –1 V instead of 0 V.

Reflection due to impedance mismatching when there’s no termination causes this obvious overshoot and undershoot. Such a circumstance can damage the I/O of the driver and receiver. Therefore, minimizing reflection is the most important task for clock distribution. The key is to properly terminate the trace.

There are multiple ways to terminate a transmission line. But for clock distribution, the most common methods are perhaps series termination, parallel termination, Thevenin termination, and ac termination. Only series termination is done at the driver side. The other three eliminate the reflection at the receiver end.

Series termination involves directly connecting a resistor in series with the driver output pin and the trace (Fig. 2a). The value of the series resistor is chosen so its sum plus the output impedance of the driver equals the characteristic impedance of the transmission line (ZO). In most designs, a value of R = 25 to 30 Ω is recommended and can be determined by measurement.

Series termination is chosen when the driver output impedance is smaller than ZO. For most transistor-transistor logic (TTL) or low-voltage CMOS (LVCMOS) drivers, this is the case. Series termination also has no dc current to ground, so it is a low-power solution. But the rise/fall time slows down and, thus, there’s less jitter immunity. The TTL or LVCMOS driver should drive a small number of devices located at the far end.

Parallel termination is when a resistor is connected at the end of the trace to ground, in parallel to the input circuitry of the receiver (Fig. 2b). It’s simple but consumes the most power of all four methods.

For Thévenin termination, two resistors are connected in series from power to ground at the end of the trace (Fig. 2c). It consumes less power, but requires two components.

The most commonly used sink termination method for clocks is ac termination, since it doesn’t consume dc power (Fig. 2d). Yet with an added capacitor, propagation delay is larger. The resistor values are usually chosen to be larger than 50 Ω to counter the leakage to the input stage of the receiver.

For example, 75 Ω is typically used. The capacitor value should be bigger than 50 pF to effectively sink ac current. A higher capacitor value enables heavier ac sink, but consumes more power. Also, to ensure decent transition edge of the clock, a value between 100 and 120 pF is recommended.

All of these methods can be applicable to different scenarios. Choose wisely, keeping the above pros and cons in mind, and experiment.

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Proper termination addresses the clock signal integrity. The second issue is getting its interference with other components under control. Due to its periodic nature, clock spectrum contains very concentrated energy at its fundamentals and harmonics. These narrow-band energies are a good source of radiation. When it needs to travel a long distance over the board, it can be a major source of interference.

UNDERSTANDING EMI EMI is any electromagnetic disturbance that interrupts, obstructs, or otherwise degrades the effective performance of electronics. The disturbance can come from the system itself or from other systems. Therefore, any electronic system becomes the source and the recipient of EMI simultaneously. With the widespread use of electronic equipment in daily life, standards and legislation have been defined to ensure that different electronic devices can be used in parallel without influencing each other’s function.

There are two types of EMI mechanisms: conducted and radiated. Conducted EMI is the unwanted coupling through parasitic inductance/capacitance that exists between signals or through power or ground connections. For clock frequencies lower than 30 MHz, EMI is typically manifested as conducted EMI. Radiated EMI is the unwanted interference directly through electronic/ magnetic radiation, and it is dominant with clock frequencies higher than 30 MHz. Based on these two mechanisms, you can reduce EMI several ways: shielding, decoupling, careful layout, and changing signal source characteristics.

Shielding uses conductive material to wrap up the EMI completely to ground. This keeps electromagnetic energy inside the system. It also makes it harder for an external signal to create EMI in the system. Shielding is useful for both conducted EMI and radiated EMI. However, it doesn’t work well in some cases.

The radiation’s efficiency depends on the height above the ground or power plane, in addition to the length of the conductor in relation to the wavelength of the signal component (fundamental, harmonic, or transient such as overshoot, undershoot, or ringing). At lower frequencies, radiation is almost exclusively via I/O traces. RF noise gets onto the power planes and is coupled to the line drivers via the VCC and ground. The RF is then coupled to the trace through the driver as common-mode noise.

Since the noise is common mode, shielding has very little effect, even with differential pairs. The RF energy is capacitively coupled from the signal pair to the shield, and the shield itself does the radiating. One cure for this is to use an RF choke to reduce the common-mode signal. Good decoupling and layout can reduce EMI more effectively than shielding.

Decoupling capacitors on each active device (connected across the power supply as close to the device as possible) provides low ac impedance path to ground. It helps to guide the high-frequency clock component directly to ground rather than interfering with other signals.

A general approach is to use multiple capacitors at values of two decades away so the combined ac response covers wider frequency range, for example, 0.1 µF and 1 nF. Place the lowestvalued capacitor as close as possible to the device to minimize the trace’s inductive influence. This is especially important for small capacitor values because the trace’s inductive influence is no longer negligible. It is always a good idea to have a place holder for decoupling components on the board. Make sure that the signal flows along the capacitor (Fig. 3).

For layout, the basic principle is to keep the ac return path short and minimize the signal loop. It has proven to be effective to go for a dedicated ground plane and multi-layer layout. Embedding the clock signal between two ground traces is also useful, though this increases cost of the board. For cost-sensitive designs such as portable systems, it’s not desirable.

Unlike these methods, which passively bypass EMI, changing the clock signal itself helps actively reduce the EMI generation and is much cheaper and flexible. One way is by wave-shaping with series resistors to control the rising/falling edge of the clock. Slowing the edge usually reduces the number of high-frequency components and their energy. Many clock generation ICs offer edge-control capability. A more popular method is to adopt spread-spectrum clocking. For more information, check out the video about EMI reduction at www.ti.com/emireductionvideo-ca.2

SPREAD-SPECTRUM CLOCKING Spread-spectrum clocking (SSC) simply alters the clock spectrum by spreading the concentrated clock energy over a wider frequency band, which effectively reduces the peak energy. If the system under test radiates all of its energy at one frequency, this energy falls into a receiver’s single-frequency band, which will register a large peak at that frequency over the limit.

SSC distributes the energy so it falls into a large number of the receiver’s frequency bands, without putting enough energy into any one band to exceed the statutory limits. For electronic equipment with sensitivity to a narrow band of frequencies, SSC helps generate less interference. On the other hand, equipment with broadband sensitivity to EMI will experience more interference.

Figure 4 demonstrates a clock’s spectrum before and after spreading. After SSC, the energy is more evenly distributed with no peak above the allowed limit. Design parameters for SSC include:

Modulation index d: the amount of frequency variation (or spread) as a relative percentage of the desired clock frequency, fc. The more d, the more that EMI will be reduced. However, more jitter will also be added into the clock. For example, ±1% spread means that a 100-MHz clock is spreading from 99 to 101 MHz.

Modulation frequency fm: the rate the clock frequency is modulated between fc and (1-d)fc. Using the same example as above, fm decides how fast the clock will change from 99 to 101 MHz. Usually, fm is selected to be larger than 30 kHz so it doesn’t interfere with the audio band, while it’s small enough not to impact the normal operation of the system itself.

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• Modulation profile: specifies how the clock frequency is modulated between fc and (1-d)fc in the time domain. The best sweep profile, shaped like the popular “Hershey’s Kiss” chocolate treat, generates an evenly distributed spectrum. Since it’s hard to create this profile, most of the time a triangle sweep is used. Triangle shapes don’t create a completely even frequency spectrum, resulting in ripples at both “ends” of the spread (Fig. 4, again).

• Spread type: down spread or center spread. Down spread expands the clock frequency to lower the band, for example, from 98 to 100 MHz. Center spread evenly distributes the spectrum centered around the clock frequency, such as 99 to 101 MHz. Down spread is used when the system can’t run at speeds higher than the center frequency.

The modulation profile, d, fm, and spread type determine the total EMI reduction. Figure 5 shows the EMI reduction amount versus the above key parameters using CDCE949 as an example. SSC can be easily implemented with today’s IC technology. It is built into a lot of clock generator products, such as CDCS502,3 and can be turned on/off. Also, the settings can be changed on the fly through I2C, SPI, or pins. It has become more popular, especially in portable electronics devices, because of faster clock speeds and smaller devices.

Because these devices are designed to be lightweight and inexpensive, passive EMI reduction measures such as capacitors or metal shielding aren’t viable options. Active EMI reduction techniques like SSC are preferred, but can also create challenges for designers. Modifying the system clock runs the risk of the clock/ data misalignment. Therefore, understanding the key parameters and their impact is needed.

In summary, high-speed clock distribution isn’t an easy task and requires good understanding of the different methods and tradeoffs. Good matching and layout design is fundamental. EMI is a complex problem, and it can’t be fully predicted before board development. Nonetheless, some guidelines can be followed in advance to counter its effect. Using SSC is an easy, fast, and low-cost option to control clock-induced EMI. However, remember that SSC will increase jitter and not all receivers are able to handle it.

References:1. Wieler, Alexander, and Pakosta, Alexander, “High-Speed Layout Guidelines,” Application Note – SCAA082, Texas Instruments, November 2006; www.ti.com/scaa082-ca

2. Wu, Lin, “EMI Reduction” videocast; www.ti.com/emireductionvideo-ca

3. “Crystal Oscillator / Clock Generator with optional SSC,” CDCS502 Datasheet – SCAS868, Texas Instruments, December 2008; www.ti.com/cdcs502-ca

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