Altera recently completed interoperability testing between its Stratix IV GT FPGA and MoSys’ Bandwidth Engine device in a serial memory application. Stratix IV GT FPGAs leverage the GigaChip Interface to interoperate with the Bandwidth Engine. Thus, designers of 100G wireline applications, such as traffic management and packet processing, will be able to implement a high-performance, high-bandwidth memory solution, according to the company.
Altera is a founding member of MoSys’ GigaChip Alliance. The alliance is a collaborative effort among semiconductor companies to enable highly efficient serial chip-to-chip communications in next-generation, high-performance networking, computing, and storage systems.
So far, it’s borne fruit with the GigaChip Interface. It’s a short-reach, low-power serial interface that enables highly efficient, high-bandwidth, low-latency performance.
Stratix IV GT FPGAs support the GigaChip Interface through the device’s soft memory controller, which helps maximise design flexibility, and its 11.3Gbps transceivers. With this support, customers can increase system performance while minimising board costs and pin counts.
