LPC11U1x architecture
NXP has extended its USB portfolio with the 32-bit LPC11U00 family (Fig. 1). This chip is based on Arm's Cortex-M0 core. It can have up to 32 Kbytes of flash and 6 Kbytes of SRAM. The SRAM includes a 2 Kbyte, dual-port USB buffer allowing applications to trade off space between buffering and application data as necessary. Drivers and boot code are included in ROM to reduce the flash code requirements.
The chip targets a range of applications from mobile accessories to industial and consumer USB-based devices. The 32-bit architecture provides a performance boost over 8- and 16-bit alternatives while providing one of the lowest active and inactive power curves.
The chip is priced at $0.99 in quantity. It is available in a 4.5mm by 4.5mm TFBGA48 but it only uses two rows of balls. This allows it to be used on dual layer boards to reduce cost. A chipscale package will be available in the future. It is in the 2.5mm range in terms of size but its 64 bump QFN package will require a more expensive 8 layer board. The chip is also available in LQFP48 pachages. It is pin compatible with the LPC134x series.
NXP's USB module will be included on all new micros since it adds less than $0.10 per chip. It has a dedicated PLL allowing the core to run at a different speed to reduce power consumptin. The module supports up to 10 physical endpoints allowing the chip to logically link its range of interfaces via individual endpoints. It also supports USB SoftConnect.
The other interfaces on-chip include 2 SSP, I2C, and a UART with SCI support for handling Smart Cards. On the analog side there is an 8-channel, 10-bit ADC. These peripheral ports are shared with 40 GPIO pins.
The chip provides a range of power profiles. These are directly accessible via C APIs. It supports USB wake up from deep sleep. It supports supply voltages from 1.8V to 3.6V.
