How do I combine Spice, IBIS, S-parameter, package, and pc-board models?

With many board designs incorporating multigigahertz interconnect speeds, vendors often supply encrypted transistor-level Spice models rather than IBIS models. Designers must work with suppliers to obtain consumable models that will fit with their specific design environment.

How do I efficiently enforce constraints in today's high-speed pc-board designs?

First, you must decompose your design into a finite number of signal classes. Through simulation, you derive the relative constraints for each of these signal classes. A constraint-driven design methodology lets you combine those constraints into your physical database to drive layout and facilitate design-rule checking.

How do I close on timing?

The challenge here isn't extracting delays from the physical layout. Rather, the challenge lies in exporting the enormous amount of data that results to spreadsheets and other mechanisms for examination, sorting, and analysis. Designers need a constraint-driven design methodology to update constraints and edit and update the design itself.

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