Infineon and Delta Join Forces on Vertical Power Delivery for Data Centers
Infineon expanded its existing collaboration with Delta Electronics to develop state-of-the-art vertical power delivery (VPD) modules that can supply power to AI chips in data centers more efficiently.
The companies said the partnership brings together Infineon's robust silicon MOSFETs and embedded packaging expertise with Delta's extensive power-module design and manufacturing capabilities. Delta leverages Infineon's OptiMOS 90-A integrated power-stage solution for the new modules, which will be designed to supply power vertically rather than horizontally to reduce power losses in the PCB as well as the associated heat.
Adam White, President of Power and Sensor Systems at Infineon, said the tie-up is targeted at hyperscalers and other tech giants grappling with growing power needs of AI training and inferencing. “The close collaboration with Delta is a perfect example of complementarity. Together, we're offering tangible value to the hyperscalers, maintaining high efficiency and robustness while reducing cost and further driving decarbonization.”
Artificial Intelligence: Why is It So Power-Hungry?
Today, the most advanced graphics processing units (GPUs) and tensor processing units (TPUs) for training large language models (LLMs) can contain more than 100 billion transistors based on 3- or 4-nm process nodes. Even though these chips use increasingly small supply voltages — usually less than 1 V — they can require currents that are trending up to more than 2000 A. This pushes their continuous power demand, also called the thermal design power (TDP), to new highs. For instance, NVIDIA’s Blackwell GPU burns through 1200 W, and the Blackwell Ultra consumes up to 1400 W.
To supply all of that current, the chips are typically surrounded by voltage regulator modules (VRMs) that flank the north and south sides or the east and west sides of it. These DC-DC converters send power laterally over the last several centimeters of a power delivery network (PDN) while carefully regulating supply voltage to the load.
To reduce voltage ripple when the processor leaps to full power, decoupling capacitors are placed under the SoC on the other side of the PCB. And inductors are placed above to filter out noise and smooth out the output voltage from the VRM.
But the downward trend of voltage scaling and upward trend of current poses challenges for the lateral power delivery (LPD) model.
One of those challenges is power loss, which has thermal implications. While the voltage regulators are placed as close as possible to the load, they need to push a large amount of current laterally through the resistance in PCB traces, causing resistive (I2R) losses.
These losses add up even over short distances due to the ultra-high currents used by high-performance AI chips. They also generate heat that must be removed before it saps the system’s performance. Plus, the localized thermal gradients of the processor risk warping the PCB.
Traditional power approaches are also inadequate due to increasingly tight space constraints. As GPUs and other AI chips burn through more power, companies add more power devices, magnetics, and passives around the processor to handle it all. This poses difficulties due to the limited space in the system. However, it increases the number of power lines to the load, too, which means the power encounters more PCB resistance.
These DC-DC converters must handle the highly dynamic nature of AI workloads, which can result in larger step changes in current also known as load transients — di/dt, for short. These transient currents can create stress within the PDN, and if the amount of current rushing into the AI chip suddenly rises, say, to run at faster clock frequencies or handle different parts of the AI training process, voltage drop can occur. Also called IR drop, the sudden decrease in voltage can take a toll on the chip’s performance and efficiency.
However, traditional power technologies don’t possess the speed to handle these load transients. The reality is that chips used in AI training can require approximately 3 mF of decoupling capacitance as close as possible to the processor to store energy and release it when the load changes too suddenly for the DC-DC converter to keep up. In most cases, vast clusters of multilayer ceramic capacitors (MLCCs) are placed directly under the load. These components occupy the most power-sensitive real estate on the PCB, though.
Vertical vs. Lateral Power Delivery
Infineon and Delta are trying to cut through these challenges by replacing lateral with vertical power delivery.
In VPD, voltage regulators are placed underneath the processor by displacing the decoupling capacitors under there today. Feeding power up through the PCB instead of across it reduces trace lengths and the resistance in the power’s path, helping cut down resistive losses and the resulting heat. The closer placement means that the VRM can respond faster to sudden load steps, minimizing the requirements for capacitors and inductors in the PDN.
Infineon said the approach also helps enable higher power density. By making sure more power reaches the processor, VPD modules don’t need to be oversized to account for power losses in the PDN. In many cases, vertical power modules feature the capacitors embedded inside the package, while the inductors are placed on top of the block to increase power density and more efficiently power CPU, GPU, SoC, and memory rails.
Furthermore, the vertical power delivery design frees up space on the PCB to reuse for high-speed signal routing or additional components like high-bandwidth memory (HBM) stacks that surround high-end AI chips.
Delta is developing vertical power modules with Infineon's silicon OptiMOS integrated power-stage solution. The power stages must be paired with multiphase digital controllers to build a complete DC-DC converter.
Infineon has been upgrading its integrated power stages from the inside out. Last year, it revealed the thinnest silicon power wafers in the world with a thickness of 20 µm, which is around half as thick as current state-of-the-art power wafers. By reducing substrate resistance by 50%, the company said the ultra-thin wafer technology minimizes power losses by 15% at the system level.
The tech is a boon to vertical power delivery because it underpins Infineon’s vertical trench MOSFETs, which allows for a closer connection to GPUs or other AI chips.
“Our collaboration has resulted in the development of highly advanced VPD modules, which allows us to provide unparalleled power efficiency, reliability, and scalability for our customers,” explained Ares Chen, VP and GM of the power and system division at Delta.
Delta is working more closely with semiconductor companies to support the power needs of AI and other new innovations. The company recently partnered with Microchip Technology to adopt silicon carbide (SiC) devices in its designs.
Delta and Infineon are also among the companies working with NVIDIA on its future high-voltage DC (HVDC) power architecture, which is widely seen as a leading solution to the increasing densification of server racks.
