Stackable POL Converter Module Powers Processors from Below

A stackable point-of-load (POL) converter recently introduced by TDK can supply up to 200 A in an ultra-compact package, enabling vertical power delivery for ASICs, FPGAs, and other SoCs in data centers and at the edge.

The FS1525 is the latest power module in TDK’s µPOL converter family, delivering up to 25 A with fast transient response, minimal voltage ripple, and low spectral noise. At the same time, several of the µPOLs can be stacked or placed in parallel to deliver up to 200 A with current sharing.

TDK said the entire power module measures 3.8 mm tall. That means it can fit under the same heatsink as the processor or even underneath the circuit board to enable vertical power delivery (VPD).

Featuring a wide range of input voltages from 4.5 to 16 V and adjustable output voltages from 0.6 to 1.8 V, the µPOL is optimized for powering AI-class processors, including the core voltage rails in 3- to 6-nm ASICs, which typically run on very small operating voltages of less than 1 V.

The modules can also be used to supply secondary power rails flowing into the I/O, memory, and other blocks within the processor. TDK said that SerDes requires more stable power delivery than most blocks with sub-5-mV peak-to-peak ripple.

With kilowatt-class GPUs, CPUs, and other data center chips pulling far more than 1,000 A through their core power rails, a number of companies and startups such as Analog Devices, Infineon, and Texas Instruments are rolling out advanced multiphase power modules and integrated voltage regulators (IVRs) to manage it all. However, TDK is positioning its µPOL DC-DC converters to supply the growing number of auxiliary power rails in ASICs, FPGAs, and other SoCs, complementing the core power providers.

µPOL Mirrors Traditional DC-DCs in a Compact Package

Using its 3D chip-embedded package technology, TDK said the µPOL integrates all of the building blocks of a traditional DC-DC converter, including power MOSFETs, power inductor, bypass capacitors, controller, driver, logic, and memory into a single package measuring only 7.65 ×6.80 mm. The µPOL is small enough to fit underneath standard PCIe accelerator cards, system-on-modules (SOMs), and other boards used in VPX, SMARC, and 1U and 3U rack systems, giving flexibility to system designers.

With the increase of computing power required to run AI workloads in data centers and out at the edge, next-gen SoCs are driving demands for DC-DC converters that can provide high efficiency in tight spaces.

VPD is a relatively new approach in which POL converters are placed directly under the SoC on the opposite side of the board rather than in the congested area surrounding the processor. In lateral power delivery, current races over the PCB and into the PoL, encountering resistance in the copper traces on the PCB. That causes I²R losses to occur in the power delivery network (PDN). In some cases, the distribution losses can exceed 20% of a processor’s thermal design power (TDP).

However, the rising power demands of AI-class chips are leading to overheating and overcrowding at the board level. Delivering higher currents requires the use of complex multiphase DC-DC converters, which are becoming unmanageable, said TDK.

Each DC-DC converter in the larger power supply requires a relatively large inductor, creating tension with the tight space constraints inside servers. Placing more DC-DC converter stages in the system also means routing power through longer PCB traces. If the number of power stages is doubled — while maintaining the same spacing with the SoC — the entire power supply is technically sending current twice as far, increasing I²R losses. These longer traces, coupled with higher inductance, can cause EMI problems.

Cutting I²R Losses with Vertical Power Delivery

TDK said VPD closes the distance significantly, reducing I2R losses and the heat that comes with them. By slinging power vertically rather than laterally, it can bypass more of the inductance and resistance in the PCB, improving transient response.

These faster response times are important for AI workloads, which have highly dynamic power characteristics, siphoning large amounts of current in a very short time when leaping to full power. If the power supply can’t supply current fast enough, the voltage in the core power rail can drop suddenly. These voltage fluctuations could lead to performance degradation.

Not only can vertical power be used to keep pace with the rising power demands of high-performance chips, but it will also manage the proliferation of power rails and increasingly complex power networks in areas such as data centers. Today’s electronic systems are fragmenting into dozens or even hundreds of power rails and interdependent voltage domains, requiring more power density than ever. At the same time, the real estate available for power electronics continues to contract, imposing constraints on designers.

The challenge comes into focus in PCIe accelerator cards based on high-performance SoCs or FPGAs. These cards consume between 75 and 150 W, with the majority delivered to the core power rail. It often requires 5 to 15 discrete DC-DC converters to supply power to the core rail, which operate at 0.45 to 0.90 V and run on 25 to 150 A, according to TDK. Add the voltage regulators used to route power to the SerDes and other subsystems, and the result is a densely packed power tree competing for every square millimeter of PCB.

Streamlining with SESUB

TDK is trying to relieve the pressure by moving power delivery under the PCB with the FS1525. To reduce the form factor of the module and fit it under the board, the µPOL uses the company’s semiconductor-embedded-in-substrate, or SESUB, technology. The power IC die, comprised of the power MOSFETs and gate drivers, is embedded into the substrate of the package to minimize interconnects and avoid unnecessary losses. Meanwhile, the inductors and other passives are put directly on top of it to minimize parasitic inductance.

Minimizing resistance and inductance leads to fast response and accurate regulation with fast-changing currents common in AI chips. The boot and bypass capacitors are also incorporated into the µPOL.

The FS1525 can scale from 25 A with a single µPOL up to 200 A using eight µPOLs to serve processor core voltage rails. DC-DC converters are interleaved to operate at bandwidths in excess of 10 MHz. TDK said it also features fast transient response times ranging from 10 to 200 A/µs along with low output-voltage ripple and true differential remote sensing to deliver accurate regulation directly to the processor.

Digital programmability over I2C and PMBus enables real-time telemetry, adaptive tuning, and fault management for voltage, current, and temperature monitoring, which are all crucial to keeping things under control during dynamic AI workloads. In addition to reducing parasitic resistance and inductance that can negatively impact voltage regulation, TDK said the µPOL stays cooler than most thanks to the integration of thermal vias in the package. Junction-to-PCB thermal resistance (θ_J-PCB) is 1.4 K/W.

According the company, the FS1525 is widely used in FPGA SOMs, which tend to have 10 to 15 distinct power rails feeding into different internal domains. They include internal logic, programmable interconnects, and embedded memory on the core power rail, which requires very stable and smooth voltage regulation at high currents.

In addition, various secondary power rails connect to I/O and SerDes, among other things. These power rails demand strict sequencing, which means powering up and down domains in specific orders.

TDK said the µPOL is deployed in Altera’s Agilex family of FPGAs and several of AMD’s programmable SoCs, including the Versal Edge, Zynq UltraScale MPSoC, and Versal ACAP, widely used in AI applications.