Each of the three main custom digital IC technologies has unique attributes, and each is particularly suited to certain circumstances. FPGAs, for instance, are a good choice for very low volumes because they have low NRE and a quick timeto-market. They do, however, have a high unit cost. For high production volumes, it becomes essential to invest NRE to get the lower unit cost of a platform or standard-cell ASIC.
When there is uncertainty in production volumes or design stability, it becomes advantageous to use a platform ASIC first, followed by a migration to a cost-reduced standard-cell ASIC. This gives all of the advantages of a platform ASIC and standard cell ASIC—moderate initial NRE and quick time to market with the lower unit cost of a standard cell ASIC becoming available as volume ramps. The tradeoffs for the three design options are summarised in Figure 1.
Figure 2 shows the total cost for an ASIC design that requires no re-spins, while Figure 3 shows the total cost for the same design when two re-spins are required. With the additional cost of two re-spins, the break-even quantity for a standard-cell ASIC rises dramatically. With a migration strategy, all re-spins would be done in the platform ASIC, reducing the cost, risk and time.
Platform ASICs shorten time-to-market by using pre-built slices or base wafers that have addressed many of the complex physical aspects required in standard-cell ASIC design. Platform ASICs use fewer customisable metal layers, reducing mask NRE and re-spin costs. The benefits are magnified when a vendor provides a conversion or migration path from a platform ASIC to standard-cell ASIC. The engineering effort required to convert to a standard-cell ASIC is reduced greatly by using a vendor who offers both technologies and understands the complexities and tradeoffs involved in performing a migration.
To achieve lower unit cost in a migration, the die size must be reduced. This can initially be achieved by removing unused resources on the platform ASIC, such as unused I/Os, logic fabric, memories, PLLs, and diffused cores. Next, the conversion of the platform-ASIC logic fabric into standard-cell ASIC gates produces a further reduction: typically, standard-cell libraries are finer grained and have more routing layers, so they achieve higher utilisation. They are also normally faster at the same process node, easing timing closure issues.
Other conversion considerations include the following:
Platform ASICs typically diffuse a fixed number of memory blocks on each base, and they must be highly configurable. Small dual-port memories are more configurable than single-port or larger memories, but configurable memories are less efficient than what could be used in a standard-cell ASIC. Remapping memories to highly optimised standardcell ASIC memories, while removing unused memories from the platform ASIC can provide a significant die size reduction. Designers must be aware that there may be slight timing or functional differences between platform-ASIC memories and the compiled or latch-based memories available in standard-cell ASICs.
Platform ASICs typically address design-for-test functions such as scan, ramBIST, JTAG, I/O parametric tests, and IP core testing. The standard-cell ASIC designer, on the other hand, must implement these test functions, or use a vendor that provides this capability—the level of compatibility between the test methodologies is extremely important in achieving a smooth conversion.
Most platform ASICs have predefined clock networks. Some high-end Platform ASICs, such as RapidChip Platform ASIC from LSI Logic, have flexible clocking without a fixed number of flip-flops or pre-routed clocks. This is similar to standard-cell ASIC clock implementations and may enable a more straightforward translation from a platform ASIC to a standard-cell ASIC. In either case, the ASIC conversion must pay attention to implementing clock networks that match the timing relationships and insertion delays of the platform ASIC while meeting the design rules and testability requirements of the standard-cell ASIC.
Platform ASICs typically have configurable I/O cells that can operate as one of many different I/O standards. Standard-cell ASIC libraries usually support the same I/O standards with single-type, fixed I/O cells. The tradeoff, once again, is configurability versus die area. Die-size reduction depends on the removal of unused I/O cells and possibly on the use of smaller, fixed ASIC I/O cells.
If a standard-cell ASIC vendor can retain the configurable I/O cells, the conversion and re-characterisation effort will be minimised. If the decision is made to convert to equivalent ASIC I/O cells, all related board-level SPICE analysis should be repeated.
Since an ASIC conversion will result in a smaller die, a custom package cavity design is usually required, and care should be taken to minimise the difference in package parasitics to reduce re-qualification work. Special care should be given to extremely high-speed I/O interfaces such as DDR2.
The locations of I/Os in the platform ASIC should be planned to minimise die size and maintain pin compatibility. An equal number of I/Os should be used on each edge of the die and unused I/Os should be dispersed symmetrically with consideration given to the staggered pad or flip-chip I/O layout.
High-level, complex intellectual property cores can be a major obstacle in design conversions. Soft IP can be re-synthesised or translated in the same way as other logic. Hard or diffused IP cores are more difficult to translate. Very-high-performance cores with critical interface timing, such as DDR2 or Serialiser/Deserialiser (SERDES), are the most difficult to migrate. Options for the conversion of complex IP include:
- Using an equivalent IP core if available in both the platform ASIC and the standard-cell libraries.
- Redesigning/replacing the IP core with a compatible function.
- Using exactly the same IP core on both the platform ASIC and the standard-cell ASIC. This is by far the best choice. The platform ASIC may use a different power grid methodology than the standard-cell ASIC, requiring a change in the connection to the power structure, but the vendor will have a procedure for this.
Short of using exactly the same IP core, a co-design strategy should be used during the original design to mitigate the risk of subtle incompatibilities during the conversion. The IP that will eventually be used in the standard-cell ASIC should be designed-in and verified at the same time.
In summary, the conversion of IP cores, memories, I/Os and clocks all involve a common tradeoff of engineering effort versus die-size reduction. It is possible to design a completely new standard-cell ASIC and fully optimise everything. However, in the case of a platform-ASIC migration, the goal is to minimise repetition of the design and qualification effort that's already taken place, while achieving a cost-reduced, fully compatible design. Removing unused resources, converting logic to standard cells, and re-mapping memories to compatible but more efficient memories typically achieves over 90% of the potential cost reduction. Using the same I/O cells and the same IP cores minimises risk from incompatibilities and effort in conversion and re-qualification. A vendor who offers complementary platform-ASIC and standard-cell-ASIC products can provide everything necessary for a successful conversion.