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Electronic Design

Adjunct Bus Connects With PCI At 2 Gbytes/s

Standard parallel buses have run out of steam. Faster ad-junct buses are needed to provide high-speed supplemental peripheral system interconnects. One such bus, the HyperTransport (formerly the LDT bus), delivers a 2-Gbyte/s alternative connection mechanism for processors, peripherals, and boards.

Developed by AMD of Sunnyvale, Calif., and API Networks, HyperTransport follows in the footsteps of emerging adjunct buses, such as the front-panel data port (FPDP) bus. It's not a standard parallel board or module bus. Instead, it's an asynchronous (self-clocking), unidirectional, point-to-point device that can be daisy-chained for multiple connections. This pseudoserial bus uses fast serial, differential connections in 2-, 4-, 8-, 16-, or 32-bit widths. A bidirectional link requires two separate 1-Gbyte/s bus connections, one each way.

Bus overhead is low, though, as there is no arbitration or bus turnaround delay. Bus data is ordered in 2-byte packets that are serialized if necessary onto the pseudoserial links. Up to 32 connections can be daisy-chained together. Data is passed down the chain until it reaches the addressed port.

Provided by API, the AP1011 offers the first HyperTransport-to-PCI bridge implementation. It lets designers deploy the HyperTransport bus bridged to the standard PCI peripheral bus. On one end, it implements two 8-bit wide, 533-MHz (clocked on both edges) HyperTransport paired ports—two sets of I/O ports. On the other side, it supports a 32- or 64-bit PCI 2.2 bus port at 25 to 66 MHz.

The AP1011's HyperTransport port pairs support bidirectional links to upstream and downstream connections. When packets arrive addressed to the port, they're buffered and passed on down to the PCI bus connection. If the packets do not address the port, they're passed on to the next HyperTransport link. Passing the data takes 70 ns. Each HyperTransport link takes 55 pins.

The PCI bus side has a built-in PCI arbiter that supports up to six PCI bus devices. It can be configured as an external arbiter for the PCI bus proper. The chip supports 5- and 3.3-V PCI bus operation. For 66-MHz, 64-bit PCI operation, it can drive two slots. For 33-MHz, 32-bit operation, it drives four PCI slots. The chip's internal I/O queues buffer transactions to and from the PCI bus. These queues include posted writes and delayed requests for PCI-originated transactions.

The AP1011 comes in a 352-lead SBGA. It uses LDT differential signaling for the bus, with a 600-mV swing, centered on 600 mV. The chip costs $95 each in quantities of 1000. Sampling now, production begins in June. API also is licensing its HyperTransport interface as IP for ASICs.

API Networks, 130C Baker Ave. Extension, Concord, MA 01742; (978) 318-1100;

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