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FPGAs Deliver Key Stages For 10-Gbit Ethernet

It may not be here yet, but 10-Gbit Ethernet is coming. Key components for its implementation over optical networks are now emerging, like two FPGAs from Lucent Technologies: the ORLI10G 10-Gbit Ethernet line interface and the ORT82G5 eight-channel 1.25/2.5/3.125-Gbit/s serializer/deserializer (SERDES). These devices incorporate hard standard-cell logic for the Ethernet components and FPGA logic gates to implement a full design.

Called FPSCs, FPGAs integrated with standard-cell logic, both are built on Lucent's ORCA 0.13-µm 7-level metal COM2 CMOS process. The ORLI10G integrates a 10-Gbit serial-bus interface to optical transponders, supporting them with 400-kgate FPGAs. The ORT82G5 SERDES packs 10-Gbit channels (the XAUI) with 600k FPGA gates. The channels operate at 1.25, 2.5, or 3.5 Gbits/s for a total peak bandwidth of 20 Gbits/s.

The chips provide physical-layer line-card and transceiver backplane connections for 10-Gbit/s Ethernet. Missing is the IEEE-802.3ae 10-Gbit/s Ethernet LAN PHY, which is still undergoing standards definition. The ORLI10G offers an interface between the WAN line interface and the system interface, such as a 10-Gbit/s SONET/SDH (OC-192/STM-48), optical transport networks (OTNs), and 10-Gbit/s Ethernet. The ORT82G5 supplies the transceivers for interdevice links across a backplane or on a board.

The ORLI10G provides a 10-Gbit/s OIF (OIF 99.102.5 standard) XSBI transmit and receive interface. Line data is presented as 16-bit LVDS signals, clocked at up to 667 Mbits/s per line. The data can be clocked down to 167 MHz (1/4 line rate) or 84 MHz (1/8 line rate) or less for transfer to the on-chip 400k logic gates. The IC supports the Ethernet physical-coding sublayer (PCS). It also interfaces to the Ethernet physical-media attachment (PMA), as well as to the proposed Ethernet PHY.

The ORT82G5 implements eight 3.125-Gbit/s (2.5-Gbit/s data rate) channel transceivers with a full-duplex synchronous interface with built-in clock and data recovery. Its backplane supports SONET data scrambling/descrambling, or 8b/10b data encoding/decoding, as well as SONET framing and transport-overhead handling. Data is presented to the internal FPGA logic on an 8-bit SONET or 8b/10b parallel internal bus. Internal 10-Gbit/s XAUI features include the serial-management interface and elastic store buffers.

Designers get up to 600k gates and 111-kbit RAM for the ORLI10G, as well as 600k gates and 147-kbit RAM for the ORT82G5. The logic voltage level is 1.5 V. The chips are expected to ship in January and March, respectively. Pricing starts at $195 and $365 each, respectively, for 50,000-unit lots.

Lucent Technologies, 555 Union Blvd., Allentown, PA 18103; (800) 372-2447;

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