Electronic Design

MIPS On-Chip Debug Hardware

One of the first RISCs, the MIPS architecture has come a long way in sophistication and performance. It's a mainstream architecture licensed by MIPS Technologies to chip and FPGA vendors. MIPS made its mark as a compact, high-performance CPU in telecom, printer, peripheral, and embedded servers. It now supplies ICs, microprocessors, microcontrollers, and ASSPs, plus ASIC cores.

MIPS CPUs come with software debug support. But with its deployment as an ASSP, microcontroller, and ASIC core, MIPS on-chip debugging resources now include the EJTAG and PDTRACE modules. EJTAG provides a full JTAG/TAP-based debug resource, and PDTRACE supports EJTAG with a full-trace capability for instructions and data.

The MIPS breakpoint instruction BREAK causes an exception, as does special trap instructions and optional watch registers. The watch registers can be programmed to cause specific exception on any access, or store to a specific 64-bit double word. Also, an optional TLB-based MMU can be programmed to trap on any access, or more specifically, on any store to a page of memory. These need a software monitor to modify program memory, insert breakpoints, and perform other functions.

The Debug Mode is entered by a debug exception, which can be caused by the Debug Breakpoint instruction (SDBBP), a single-step feature after an in-struction execution, a hardware breakpoint on in-structions or data, or a debug interrupt (EJ_DINT signal or by the TAP interface).

The Debug Mode is exited via the Debug Exception Return (DRET) instruction. The debug hardware contains three registers (DEBUG, DEPC, and DE-SAVE) in the MIPS Coprocessor 0 register set.

EJTAG supports off-board JTAG memory. In the Debug Mode, the CPU can reference I or D not in the system under test. The EJTAG memory is mapped to the processor as physical memory, but the references are converted into TAP transactions. The new EJTAG instruction SDBBP puts the processor into the debug mode and can fetch associated handler code from EJTAG memory. A memory-mapped debug memory segment (dmemseg) also is available as a subsegment of the debug memory segment (dseg).

EJTAG builds on the EJTAG/TAP interface. In the Debug Mode, users can modify memory or registers, as well as execute instructions from the host. EJTAG includes the TAP interface/controller, a hardware breakpoint unit, and a Debug Control Register. The CPU can come up in the Debug Mode; the EJTAGBOOT and NORMALBOOT set if you get a debug interrupt at reset.

The optional hardware block PDTRACE provides a trace capability for MIPS cores. It requires a Trace Control Block (TCB) to work. The TCB is the interface to the probe and outside the chip. It provides an optional Trace Buffer and does compression. It's currently under development. The Trace Control Register controls the PDTRACE hardware. Setting a bit in the register turns on various trace capabilities. PDTRACE should be able to support full trace at processor execution speeds for at least instruction trace.

The instruction trace monitors instruction execution and signals changes in the PC. It doesn't have to output each instruction address accessed, only the deltas that change program trace blocks. It reports PC changes for mispredictions, like branches that didn't follow predicted behavior some 5% to 15% of roughly 20% of the code (for minimal bandwidth), or all changed PCs. PDTRACE supports a 16/32-bit Trace Bus to the TCB. Periodically, PDTRACE syncs trace addresses to the TCB. Data addresses are compressed as well.

PDTRACE supports multiple pipelines (multi-issue CPUs). The set of output signals is duplicated for each pipeline. The instruction issues are coordinated; all instructions issued must be completed (or squashed) before the next set of issued trace data is accepted.

Trace can be implemented with either an on-chip or off-chip trace memory. The trace memory is fed by the TCB and sits between the TCB and the emulation probe. It can be implemented in the probe itself. The trace data is compressed and needs post-processing software to reconstruct the dynamic program flow for debugging.

See associated figure

  • To 15 instruction comparators
  • To 15 data comparators
  • JTAG/TAP port
  • Debug Mode
  • Soft breakpoint supported by CPU instructions
  • Data breakpoint on address and value
  • TAP scan chain to load instructions, read/write memory, registers

  • Separate trace unit
  • TCB does compression, I/O interface
  • Traces PC, data load/store addresses, and data
  • Supports MIPS, MIPS16 instructions
  • Supports I, D breakpoints/watchpoints
  • Reports PC addresses for mispredictions
  • Compresses trace data, provides periodic synchronization
  • I, D breakpoints can be used t set a trigger point

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