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Electronic Design

RapidIO Gets Chip Traction

RapidIO is rapidly becoming a chip reality. Chips are emerging that implement RapidIO connectivity. Also, a RapidIO serial bus implementation promises to build on the InfiniBand/Gigabit-Ethernet serial bus base.

RapidIO is a lower-level switch fabric for chip- and board-level switch interconnects. Its high-performance connection replaces or supplements the standard multidrop bus. RapidIO's fabric builds on a pseudoserial interconnect with widths of 2, 4, 8, or 16 bits using standard LVDS signaling. It delivers a 250-Mbit/s to 2.5-Gbit/s bandwidth per pin. And, its layered architecture­Physical, Transport, and Logical­supports memory mapping and message addressing.

Motorola's MPC8540, the first RapidIO microcontroller chip with a port, is an 8-bit, 16-Gbit/s RapidIO port controller with a 600-MHz to 1-GHz e500 PowerPC (book E) processor core and 256 kbytes of L2 cache. It has dual Gigabit Ethernet controllers, Fast Ethernet and 64-bit PCI-X controllers, a DDR external memory controller, a four-channel DMA engine, and a dual UART serial port.

Tundra is fielding three RapidIO interface chips in the first half of 2002; the Tsi400, Tsi500, and Tsi890. The Tsi400 bridge interfaces to 64-bit/133-MHz PCI-X or 66-MHz PCI and RapidIO (8-bit, 16-bit) buses. Built around an internal switch fabric, its x8 port supports 1-Gbytes/s; the x16 port 2 Gbytes/s.

The Tsi500 six-port switch node has two 16- and four 8-bit ports that interconnect through an on-chip nonblocking switch fabric. The Tsi890 switch, a general nonblocking I/O chip set for PowerPCs, integrates a PCI-X/PCI bus (64-bit/133-MHz PCI-X or 66-MHz PCI0), 8x RapidIO port, PowerPC MPX, 60x bus interface (36-bit address, 64-bit data), a DDR (64- to 72-bit/266-MHz) memory controller bus, and dual Fast Ethernet ports.

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