Edge AI Reinvents Logistics for Industry 5.0
Key Highlights
- Industry 5.0 emphasizes collaboration between humans and intelligent machines, moving beyond the automation focus of Industry 4.0.
- Edge AI enables low-latency, offline decision-making while maintaining data privacy and security by processing data locally on devices like the NXP FRDM-IMX93.
- The prototype system uses object detection AI to classify package sizes, demonstrating practical applications of AI at the edge in logistics workflows.
- The NXP FRDM-IMX93 board combines energy-efficient processing with hardware acceleration for machine learning, supporting real-time, secure edge applications.
- This approach enhances manufacturing flexibility, safety, and resilience by integrating human judgment with intelligent automation in smart workflows.
By Michael Parks, PE, for Mouser Electronics
Published June 26, 2026
Modern manufacturing and logistics are evolving rapidly, driven by the growing demand for faster, more accurate, and highly flexible operations. Traditional automation, while powerful, often lacks adaptability when systems encounter variability or unforeseen errors, such as missing barcodes or damaged shipping labels. This is where Industry 5.0 principles come into play.
Unlike Industry 4.0, which emphasized total automation and connectivity, Industry 5.0 focuses on collaboration between human operators and intelligent machines. The goal is to combine the precision and speed of automation with human judgment and flexibility, creating workflows that are smarter, safer, and more resilient. At the core of this collaborative model is the deployment of machine learning (ML) at the edge, which involves integrating artificial intelligence (AI) directly at the source of data (i.e., the edge) rather than relying on cloud-based processing. Edge AI enables low-latency and offline decision-making and keeps sensitive data local, addressing privacy and security concerns.
This article presents a prototype of a smart system built on the NXP Semiconductors FRDM-IMX93 development board that verifies the size of a package. The system combines object detection AI, real-time operator interaction, and local processing to address real-world logistics challenges.
Project Materials and Resources
Before beginning any software development, make sure you have all required components and correctly assemble the prototype hardware. This project requires not only the core development board but also specific peripherals to handle video input, graphical output, and operator interaction.
Project Bill of Materials (BOM)
NXP Semiconductors FRDM-IMX93 development kit
Required Software and Downloads
- NXP FRDM-IMX93 Yocto software development kit (SDK): Required for the cross-compilation toolchain. See https://www.nxp.com/docs/en/user-guide/UG10164.pdf. Requires free NXP account registration.
- NXP eIQ® Machine Learning Software: Used to optimize the LiteRT (formerly TensorFlow Lite) model for the Arm® Ethos™-U65 NPU. Requires free NXP account registration.
- NXP GUI Guider
- Project source code
- Terminal emulator (e.g., PuTTY, Tera Term)
- Project GitHub repository
Additional Hardware
- PC running native Linux (Ubuntu 20.04/22.04 recommended) or Windows 10/11 with Windows Subsystem for Linux (WSL2) enabled
- Pre-programmed MicroSD card containing the Linux BSP image
- HDMI monitor
- HDMI cable
- USB UVC-compatible camera
- USB-C PD power supply (5VDC, 1A minimum)
- USB 2.0 keyboard
- USB 2.0 mouse
- USB hub
Resources
- FRDM-IMX93 Board User Manual
- NXP-iMX/libcamera GitHub
- Timesys Getting Started Guide for NXP i.MX93 EVK
Project Technology Overview
This project demonstrates a proof-of-concept package verification station that combines AI-driven automation with human decision-making. The system classifies packages into three size categories using a USB camera and a pre-trained LiteRT (formerly TensorFlow Lite) object-detection model running on the NXP FRDM-IMX93 development board (Figure 1).
Figure 1: Steps for preparing a TensorFlow model for the FRDM-i.MX93. (Source: NXP)
LiteRT is a lightweight, mobile-friendly version of the TensorFlow platform, specifically designed to run ML models efficiently on edge devices such as smartphones, microcontrollers, and embedded systems. When you deploy image recognition with LiteRT, the heavy training process is performed ahead of time (usually on a desktop or cloud server). The trained model is then converted into a compact LiteRT file that can be run on a device.
At runtime, the LiteRT model takes input data—typically an image captured by a camera or loaded from storage—and pre-processes it to match the format the model expects. This often involves resizing the image to a fixed dimension, normalizing pixel values (e.g., scaling them to between 0 and 1), and adding a batch dimension. The prepared image data are fed into the LiteRT interpreter, which uses optimized kernels to run the neural network’s inference operations directly on the device’s central processing unit (CPU), graphics processing unit (GPU), or specialized accelerators, such as on-chip neural processing units (NPUs) or vendor-specific hardware accelerators.
The model processes the input through its layers; for example, convolutional layers extract features like edges and textures, pooling layers downsample the data, and fully connected layers produce the final classification scores. The output is usually a list of probabilities indicating the likelihood that the image belongs to each possible class. The application then interprets these probabilities to produce a result, such as displaying a label (e.g., small, medium, or large) or triggering an action (e.g., lighting an LED, sounding a buzzer).
Because LiteRT models are small and efficient, they enable real-time image recognition even on low-power hardware, making them ideal for Internet of Things (IoT) devices and smart cameras. This on-device approach also improves privacy and reduces the need for constant internet connections, since all computation occurs locally without uploading images to a server.
Hardware Overview
The NXP FRDM-IMX93 is a low-cost, compact development board that incorporates an NXP i.MX 93 processor. The processor is designed for energy-efficient edge computing, with hardware acceleration for ML and secure edge applications. The board includes the following features:
- CPU: Dual Arm® Cortex®-A55 cores (up to 1.7GHz)
- Microcontroller core: Arm Cortex-M33 (up to 250MHz) for real-time tasks
- RAM: 2GB LPDDR4X (onboard)
- Storage: 32GB eMMC5.1, MicroSD slot
- NPU: Arm Ethos‑U65
- Integrated security: NXP EdgeLock® secure enclave for crypto, root-of-trust, secure boot
- Connectivity: 10/100/1000 Ethernet PHY; Wi-Fi® and Bluetooth® connectivity via M.2 socket
- USB: USB 2.0 OTG and USB 2.0 host ports
- Expansion: Dual-row, 40-pin header
- Debug capabilities: JTAG, USB debug port, and onboard OpenSDA debugger
Software Overview
This section describes the various development applications used to update, test, and operate this project. A considerable amount of software is required to run this application. This article will not repeat the NXP documentation in its entirety; however, it will highlight some key points to consider when setting up the development environment on your computer. >>>Click to read the entire article at Mouser
Author Bio
Michael Parks, PE, is the co-founder of Green Shoe Garage, a custom electronics design studio and embedded security research firm located in Western Maryland. He produces the Gears of Resistance Podcast to help raise public awareness of technical and scientific matters. Michael is also a licensed Professional Engineer in the state of Maryland and holds a Master’s degree in systems engineering from Johns Hopkins University.
About the Author
Michael Parks
Michael Parks, P.E. is the co-founder of Green Shoe Garage, a custom electronics design studio and embedded security research firm located in Western Maryland. He produces the Gears of Resistance Podcast to help raise public awareness of technical and scientific matters. Michael is also a licensed Professional Engineer in the state of Maryland and holds a Master’s degree in systems engineering from Johns Hopkins University.
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