By Alistair Winning for Mouser Electronics

Published June 19, 2026

For years, system-on-chip (SoC) design has been the path to higher integration. This path has been somewhat guided by the industry’s need for smaller and faster devices that maintain superior power efficiency. While equipping a single die with more functionality has helped meet those demands and simplified system design, as things get more complex and process nodes become more specialized, that approach is showing its limitations.

Chiplets offer a different path forward, breaking monolithic designs into modular building blocks that can be combined within a single package. These integrated devices have evolved from discrete integrated circuits (ICs) and simpler application-specific integrated circuits (ASICs) or application-specific standard products (ASSPs) toward increasingly complex SoCs. ASICs, ASSPs, and SoCs all have one thing in common: They are fabricated on a single wafer using a single semiconductor process.

This approach offered clear benefits, such as reduced size and faster time to market, but it also introduced new drawbacks that have become more pronounced as technology has advanced. The process of stitching together different pieces of intellectual property (IP) into a single entity is complex, and this complexity increases as larger, more complex functions are incorporated into SoCs. There is no guarantee that the desired IP block will be available and optimized for the specified fabrication node, which can delay optimization or require a compromise to choose a different IP block to keep the project on schedule. Since the ICs are fabricated using a specific manufacturing process on a single node, if a developer were to integrate an IP block that required a different process (e.g., a power circuit), the whole chip would have to be built on the larger node. This would hinder the performance of the digital sections and be much less efficient.

As more functionality is added, yields decrease because a single defect can render a larger portion of the wafer unusable, thereby increasing costs. At the same time, emerging technologies—such as wide-bandgap semiconductors, including silicon carbide (SiC) and gallium nitride (GaN)—cannot be easily integrated into traditional monolithic SoC designs, limiting the ability to take full advantage of their efficiency and performance benefits.

Chiplets Address the Limitations

The drawbacks have slowed the process of designing SoCs and made them more expensive, but that hasn’t deterred widespread adoption because the benefits they offer ultimately outweigh the downsides. These limitations have led to the development of chiplets as an alternative approach to system integration.

Chiplets integrate different dies together into a single package. They allow IP blocks fabricated on different process nodes to be integrated within a single package. Splitting functionality into smaller, simpler dies improves yields and gives designers more assembly flexibility. This approach also enables the integration of technologies that are difficult to integrate into advanced nodes, including wide-bandgap power devices and photonics.

Along with lower costs enabled by higher yields, chiplets lower the barrier to entry into new businesses. In some cases, they can also reduce upfront design costs through reusable IP. Organizations can choose the IP blocks they need and connect the dies through a package-level interconnect, such as an interposer (Figure 1). Also, using proven dies that already meet the qualifications for specific industries or functions makes accreditation much simpler (e.g., meeting ISO 26262 requirements, including Automotive Safety Integrity Levels (ASILs)).

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Author Bio

Since graduating with a BSc in Electronic Systems from the University of the West of Scotland in 1997, Alistair has worked in electronics media across marketing, PR, and journalism roles. During that time, he worked as the editor of Electronics Engineering, Embedded Systems Europe, EENews Embedded, Technology First, Electronic Product Design and Test, and Panel Building and Systems Integration magazines. Currently, Alistair is the European Editor of Power Systems Design and a freelance writer, specializing in electronics and engineering.