Why TOLL-8N Is Gaining Momentum in High-Power, High-Density Designs
Key Highlights
- Parasitic elements like inductance and capacitance significantly affect high-speed, high-voltage GaN device performance, leading to issues such as ringing and false turn-on.
- As voltage ratings increase to 650V, device sensitivity to parasitics and overshoot effects become more pronounced, demanding optimized packaging solutions.
- The TOLL-8N package design helps minimize parasitic inductances and improve thermal management, unlocking the full potential of GaN power devices.
For electronic engineers, device packaging is just as critical to performance and thermal management as the die or multichip assembly it contains. This is especially true as gallium nitride (GaN) power devices continue to gain adoption, placing renewed emphasis on packaging as a key factor in unlocking their full performance potential. Even small parasitic elements—such as stray inductance, capacitance, and resistance within the package—can significantly affect circuits switching higher voltages and currents at faster slew rates. As a result, engineers cannot afford to overlook the importance of optimized packaging.
This blog examines why packaging is increasingly important for 650V GaN devices and how the innovative TOLL-8N package helps enhance the performance of high-speed, high-voltage field-effect transistors (FETs) while addressing parasitic effects and thermal limitations.
Start with LCR Basics
The impact of parasitics can be understood through a simple equation that defines the relationship between inductance (L) and the rate of change of current didt:
V (t) = L didt
The use of GaN FETs does not change the basic physics. However, their extremely fast current and voltage switching (didt) means that even small parasitic values once considered negligible can now have a pronounced effect on circuit waveforms. In actual hardware, these parasitics can lead to issues such as increased power-device drain overshoot and ringing, gate bounce that may cause false turn-on, and higher electromagnetic interference (EMI) peaks.
Such effects are often missed in simplified simulations. Accurate predictions typically require nonlinear device models or explicit extraction and inclusion of parasitic elements.
Identifying the locations, types, and values of all parasitics is no simple task. Although these parasitic values are very small, their impact on circuit behavior can be substantial. They are also difficult to physically access, measure, and verify.
Many of the most harmful parasitics arise from board layout, probing techniques, grounding, and copper geometry. While these elements lie outside the direct control of the power device itself, they strongly influence the measurement process. Further complicating matters is that many parasitic parameters are not fixed, as they are with discrete inductors or capacitors, but instead can vary depending on operating conditions such as drain-source voltage (VDS).
What Changes at 650V Compared to Lower-Voltage Switching
As voltages rise from lower ranges, such as 80V to 200V and up to 650V, some design factors scale predictably while others do not. Higher power-rail voltages make devices more sensitive to overshoot, since there is less margin as the voltage approaches the VDS rating. At the same time, faster switching speeds and sharper edges increase the voltage induced by didt across any inductance. As a result, gate-drive techniques that may be sufficient at lower voltages cannot simply be scaled up–as device behavior changes with voltage and current.
Package parasitics set a practical upper limit on power-device performance. Just a few nanohenries (nH) of DC-link or commutation loop inductance can interact with circuit capacitances to produce ringing and drive VDS into potentially destructive overshoot during turn-off. In addition, common-source inductance (CSI) can distort the gate-source voltage (VGS), while gate-loop inductance feeds back to alter the effective input impedance seen by the driver, distorting the driver-current waveform.
The effects of fast dv/dt slewing can be especially problematic because they pump current through the power FET’s Miller capacitance. If the gate feedback loop has a loose time constant, which is often necessary for functional reasons, brief gate-source glitches may be enough to trigger shoot-through.
Rapid dvdt creates displacement current through the gate-drain (Miller) capacitance. If the off-state gate path impedance is too high, or if CSI raises the source potential, the gate of the complementary switch in a half-bridge can momentarily exceed the threshold voltage and cause false turn-on. This leads to shoot-through, a condition where both the high-side and low-side FETs conduct simultaneously, creating a low-impedance path directly from the power supply to ground. The resulting high-current spikes are severe enough to damage or destroy the switches.
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