EE Product News

Stacking Technology Shrinks Memory Package Sizes

An advanced packaging technology has been developed that allows the mechanical stacking of chip-scale memory devices using a fine-pitch ball grid array (FBGA) interface. Significantly reducing component packaging size compared to TSOP packages, the CS-Stack package interface consists of tiny solder balls on the bottom of the chip.Standard memory components and new memory types can be packaged using CS-Stack stacking techniques. Samples of CS-Stack packages are available now and production will begin in 2002. DPAC TECHNOLOGIES CORP., Garden Grove, CA. (714) 898-0007.


Product URL: Click here for more information

TAGS: Digital ICs
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.