PCI System Controller Is PCI 2.2 Compliant

Nov. 1, 1998
Fully compliant with PCI 2.2 specification with speeds up to 75 MHz on the local bus and I2O-Ready, the USC family of PCI system controllers offers hot swappability (as per proposed PICMG Specification), 352 bytes of on-chip FIFO, compliance with the

Fully compliant with PCI 2.2 specification with speeds up to 75 MHz on the local bus and I2O-Ready, the USC family of PCI system controllers offers hot swappability (as per proposed PICMG Specification), 352 bytes of on-chip FIFO, compliance with the PCI Bus Power management Interface Specification Version 1.0, an SDRAM controller with ESDRAM support, 3.3V operation and 5V-tolerant inputs, configurable primary master, bus master and target (slave) PCI operation and many more features essential for ease of design. These devices were developed in close collaboration with leading MIPS processor companies.

Company: V3 SEMICONDUCTOR CORP.

Product URL: Click here for more information

About the Author

Staff

Articles, galleries, and recent work by members of Electronic Design's editorial staff.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!