Universal Chiplet Interconnect Express and Design Verification
What you’ll learn:
- What is Universal Chiplet Interconnect Express (UCIe)?
- Why UCIe IP verification is important.
The Universal Chiplet Interconnect Express (UCIe) is a standard die-to-die protocol from the UCIe Consortium. It’s one of the popular interfaces for connecting chiplets together. I talked with Mayank Bhatnagar, Product Marketing Director at Cadence, about UCIe and how Cadence is supporting chip development (watch the video above).
One of the tools available to designers is the Cadence Verification IP (VIP) for UCIe (see figure). The IP is designed for integration at the IP, system-on-chip (SoC), and system level. VIP for UCIe can run on any simulator that supports SystemVerilog utilizing the Universal Verification Methodology (UVM).
Verification engineers are able to check UCIe features at each functional layer, including the PHY, D2D, and protocol level. The VIP for UCIe can be used as a standalone stack or layered options like the PCI Express (PCIe) VIP.
>>Check out more of our 2026 Chiplet Summit coverage
About the Author
William G. Wong
Senior Content Director - Electronic Design and Microwaves & RF
I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.
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