C-Based Design Suite Includes Synthesis To FPGAs

Feb. 16, 2004

Designers continue to explore algorithmic design, which lends itself well to experimentation with FPGAs as the implementation vehicle. Version 3.0 of the DK Design Suite extends functionality to include synthesis of complex C-based algorithms directly to FPGAs. With the suite's new synthesis feature, users can perform area/speed tradeoffs directly from their C algorithms for performance gains of 100% or more without requiring changes to their source code.

The Handel-C synthesis tool supports the latest devices from Altera and Xilinx as well as a number of other reconfigurable architectures. Also, it now retimes hardware-critical paths. It automatically uses FPGA combinatorial multipliers and on-chip resources. And, it automatically pipelines synchronous memory blocks.

Nexus-PDK3, the suite's co-simulation environment, has been enhanced as well. A new co-simulation manager concurrently handles multiple simulation environments. Nexus-PDK3 also manages data linking and global clocks across simulations, and it provides easier user setup. The environment supports co-simulation of cycle-accurate C, C++, and Handel-C models with SystemC, Matlab/Simulink, and VHDL and Verilog simulators.

Available in March, DK Design Suite version 3.0 starts at $2000 for the Platform Developer's Package configuration.

Celoxica Ltd. www.celoxica.com

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.