Flash Memory For Wireless Systems Accesses In 60 ns
Samples of a high-speed 64-Mbit flash memory are now available with random access times of just 60 ns and burst transfer frequency of 81 MHz. The MT28F644W18 targets mobile applications, with the memory core and I/O pins all able to operate from a 1.8-V supply. The chip’s memory architecture provides additional enhancements such as a flexible 4-Mbit multipartitioned architecture, clock suspend, and a fast programming algorithm to meet the performance demands of mobile platforms. The multipartitioned architecture allows for more partitions and supports code segmentation for different applications, yielding improved efficiency. In sample quantities, the 64-Mbit flash memory costs $7.25 apiece.
High-Performance, Low-Power CPU Outguns Pentium M
Higher instruction efficiency and faster clock speeds let the Efficeon run applications at up to 80% faster than on previous CPUs from the developer. The next-generation TM8000 CPU will initially become available in 1-, 1.1-, 1.2-, and 1.3-GHz speed grades. At those speeds, the CPUs consume 5, 7, 12, and 14 W, respectively. The processors include a new 256-bit wide very-long-instruction-word microarchitecture along with a revamped version of the company’s code-morphing software. The software allows up to eight instructions to be executed every clock cycle. The Efficeon includes three high-speed interfaces: a 400-MHz Hypertransport bus that can transfer data at up to 1.6 Gbytes/s, a double-data-rate (400 MHz) SDRAM memory bus, and an AGP-4X graphics interface.