Reflecting on the 2026 Chiplet Summit

The Chiplet Summit has wrapped up and I’m still trying to catch up with all of the things I learned at the conference. We will be posting more articles and videos in with our Chiplet Summit 2026 coverage as they’re finalized.

Where are We Now with Chiplets?

The chiplet market is large and growing, but it’s dominated by hyperscalers and high-performance computing (HPC) artificial-intelligence (AI) acceleration. This area dominates the use of chiplets for a variety of reasons that’s centered around money and the reticle limit. NVIDIA’s Blackwell family would not exist in its present form without chiplets.

AI is gobbling up resources like high bandwidth memory (HBM) that is in its fourth incarnation. The high end AI chips are surrounded by multiple HBM3 and HBM4 chiplets. These chiplet-based solutions are employing HBM from a third party but the remaining chiplets tend to be from the same source and using custom interconnects. This makes sense given the tight integration and control of both sides of the equation. The idea of an open chiplet market is a work in progress.

What About Chiplet Interconnect Standards?

The Universal Chiplet Interconnect Express (UCIe) is in its third incarnation. UCIe 3 chiplets were demonstrated at a number of booths, though these are evaluation systems. Production UCIe-based solutions are expected later this year, but they’re production-ready at this point. A number of UCIe demonstrations were held at the Chiplet Summit, such as those from Cadence and AlphaWave Semi’s AlphaChip 1600 (see figure).

UCIe has garnered a significant following and designers utilizing custom interfaces are taking a closer look at UCIe that’s become more flexible as new features are added. Now, protocols that run over UCIe are becoming more important. The ability to connect standard interfaces like AXI4, AXI-S, TileLink, CXS, and CHI over UCIe will greatly simplify the designer’s chores.

The other major chiplet interconnect standard is the Open Compute Project’s BoW (bunch of wires). BoW is probably a better choice when higher-level protocols and features like cache coherency aren’t required. It’s also good when bidirectional connections aren’t even. Often applications like image sensors need high bandwidth in only one direction. Unsurprisingly, one of the main chiplet applications these days that’s not related to AI chips is imaging.

A particularly interesting discussion concerned the lower-speed, UCIe sideband channel that can be used for management purposes. This is intriguing because, while AI chiplets focus on high speed and high bandwidth, other applications don’t require those features. For example, microcontrollers or lower-end microprocessors can benefit from a lower-speed interface.

Chiplet Market Forecast for 2031

I hosted the closing panel that looked ahead to the chiplet market in 2031. Interconnect standards and the open chiplet marketplace were major points of discussion. While most were optimistic about a marketplace in the future, the path there isn’t as clear cut as many would like to see. Established chiplet users may not benefit from standards like UCIe, but they will eventually move in that direction.

Mixing chip technologies and types is a benefit of chiplets, but it needs to be economical. Foundry support, standards, and improved technologies will help. However, these aren’t always as easy to implement as we would prefer. Development tools have improved, yet more needs to be done to handle something like a marketplace.

There’s a wide range of potential chiplets, but economics comes into play that can make success a challenge. Not all chiplets will need to be fast and scale to the max. Security, manageability, and availability will all need to be addressed in the next few years.

I’m looking forward to seeing what chiplets do this year, as well as next year’s Chiplet Summit.