If you thought that SOTs and MSOPs were the ultimate in tiny packaging for discrete semiconductors, think again. After evicting a variety of digital and analog ICs from their plastic, leadframe-based housings, chipscale packages (CSPs) are now starting to do the same for simpler semiconductor components. One recent example is International Rectifier's FlipFET MOSFET. Another is an ESD protection circuit from California Micro Devices (CMD).
This migration down the semiconductor food chain provides further evidence that CSPs are entering the packaging mainstream. That's good news because it spreads chipscale benefits (small size and lower parasitics) to more applications. If the device is a power MOSFET, then chipscale packaging will lead to lower on-resistance. In an ESD chip, like the CMD part, the result will be faster response to high-frequency transients. Plus, the part's smaller form factor will allow it to be placed closer to the source of ESD hazards.
Much of the push to CSPs comes from the space-restricted realm of wireless communications, where circuits are getting more complex and boards are becoming smaller. Tom Dugan, a director of marketing at Semtech, notes that the number of circuit-protection components required in cell phones has risen significantly. Whereas past designs called for two or three protection components per phone, current designs demand 10 to 15. In the coming months, Semtech plans to announce a chipscale-packaged ESD protection device with very low clamping voltage.
Undoubtedly, other companies are planning CSP introductions too. After all, for vendors, the incentive to develop CSP products is even greater with discrete semiconductors than it is with ICs. Peter Stonard, the director of semiconductor marketing at CMD, observes that there's a much bigger payback for discrete-semiconductor makers going to CSPs because packaging represents a higher percentage of device cost. So why have discretes been the last to go chipscale?
Die size is one reason. According to Stonard, the industry has settled on 0.65-mm ball pitches to allow CSPs to be handled by existing surface-mount chip shooters. That pitch might not pose a problem if the chip is a complex logic circuit with sufficient silicon real estate. But for discretes, turning to chipscale at a 0.65-mm pitch could require using a die that's twice as large as the one in the packaged part. Therefore, while packaging costs go down, die costs rise. But I/O counts also are a factor, so a switch to CSP does not necessarily mean a big increase in silicon.
Where a CSP requires more silicon, vendors will likely adapt their designs, either by improving device performance or by converting a single device to a dual, triple, or quad device. Even with CSPs in a standard ball pitch, though, semiconductor vendors must be sure that their customers are ready to assemble and test them. Bill Russell, a senior applications engineer at Semtech, says, "In reality, CSPs are easy to implement on a high-speed manufacturing line." But the company still has to work closely with customers to be certain that design and manufacturing guidelines are followed.
As OEMs and contract manufacturers grow accustomed to using CSPs, vendors will be able to cut back on this hand-holding and step-up CSP product development. Hopefully, customers also will be willing to upgrade their manufacturing capabilities to handle finer-pitch components, which, in turn, will help semiconductor vendors more readily migrate their parts to chipscale. As the industry learns to handle ever-smaller CSPs, visualizing these components will require either a microscope or an active imagination.