VME is one of the oldest military/commercial-off-the-shelf (MIL/COTS) buses that still has regular design wins. Its parallel backplane bus was the fastest around at one time. The VME320 standard released in 1997 runs at 320 Mbytes/s, though high-speed serial interfaces like Serial RapidIO and Gigabit Ethernet have superceded the parallel bus.
VITA, the standards group that manages VME technology, started with VME (VITA 1.0). VITA 1.5 defines VME320, or VME 2eSST. The high-speed serial platforms include VPX (Table 1), VXS (Table 2), and XMC (Table 3). VPX and VXS are board standards like VME and use 3U and 6U form factors. XMC is a mezzanine card standard using high-speed serial interfaces. It’s an alternative to the PCI mezzanine card (PMC), whch uses a parallel PCI interface.
VME and PMC with its PCI bus were relatively stable and easy to contend with. The high-speed serial interfaces are well defined, but the number of options available can be mind-numbing. The list includes serial interfaces such as Serial RapidIO, InfiniBand, PCI Express, Gigabit Ethernet, 10-Gbit Ethernet, Aurora, HyperTransport, and XAUI. Although these interfaces are all point-to-point connections, they typically work with a hub or switch.
In addition, the reduction of pins needed to deliver comparable throughput on a high-speed serial interface is significantly lower than a parallel interface like VME or PCI. This allows many boards and platforms to handle multiple connections. A single connection allows a star configuration while dual connections support a dual-star setup (Fig. 1), providing redundancy.
A full mesh requires more connections but provides maximum bandwidth. A dual mesh offers redundancy but is a very complex backplane. Even tree or inverted-tree architectures and asymmetrical designs are options that may be more suitable to some applications. For example, a radar processing system might work best with an inverted tree where many inputs are reduced to a single result, with each level of the tree handing off a smaller processed subset of data to the next level.
The options get even more complex when mixing interconnects. This complexity is compounded by the more advanced MultiGig connectors (Fig. 2) used with VXS and VPX high-speed serial interfaces like those from Tyco Electronics, which are actually multiple wafer-size circuit boards themselves. These interconnects are used on VXS and VPX boards like Curtiss-Wright Controls Embedded Computing’s 6U VPX Champ-AV6 (Fig. 3) with four Freescale dual-core microprocessors with built-in Serial RapidIO connections.
Add to all this the ability to mix and match high-speed serial interfaces, typically Ethernet with another interface, and it is easy to see how the number of options grows significantly. Designers employing VXS and VPX often require custom backplanes, taking advantage of the backplane I/O connectors available on the 3U and 6U boards and further adding to the chaos. Attaining a level of compatibility between vendors was more than a challenge. OpenVPX looks to bring a little order to the chaotic number of options.
PROFILING A STANDARD
Formerly known as OpenVPX, VITA 65 is a systems-level specification designed so boards and systems can play nicely with each other by profiling a useful subset of the available standards such as those from VITA (see “VPX Moves Forward With OpenVPX And Additional VITA Specs”). System designers can then start with a profile instead of a lower-level form factor and interconnect level.
VITA 65 came about through cooperation from board vendors such as Mercury Computer Systems, Curtiss-Wright Controls Embedded Computing, GE, and Tek Microsystems as well as customers like Boeing so designs would not be so unique that second sourcing and upgrades would be out of the question. This was often the case where designs could utilize the host of options, not to mention the customization of the I/O connections.
Some of the considerations that went into VITA 65 include backplane architectures and development chassis interconnect topologies, module-level pin designations and protocol definitions, power and system signals, and interoperability compliance issues. The specification also defines various sizes of pipes used for the serial interfaces as well as multiple logical planes for utility, management, control, and data.
Planes define logical and physical interconnets. Pipe definitions include an Ultra Thin Pipe (UTP), a Thin Pipe (TP), a Fat Pipe (FP), a Double Fat Pipe (DFP), a Quad Fat Pipe (QFP), and an Octal Fat Pipe (OFP). This matches well with most high-speed serial interfaces. Interface speeds up to 6.25 Gbits/s per signal pair are supported.
VITA 65 takes a pragmatic approach to design. It chooses certain options, possibly at the expense of others, to define how an OpenVPX system will work. This should guarantee that every single OpenVPX board will plug into an OpenVPX backplane and work.
OpenVPX has turned into a broad cooperative effort. It did not start out that way, and there were a few heated discussions along the way. A few non-disclosure agreements (NDAs) and possibly a few arrows were exchanged. The resulting OpenVPX Working Group, which has since dissolved, and standard are better for the effort that is now under VITA.
The standard is based on VITA 46/VPX and VITA 48/REDI specifications adding aspects such as air-cooled interoperability with rear transition modules (RTMs). This enables vendors to design boards that are interoperable with the competition. Customization will still be available and will differentiate platforms.
Designers can now select from a set of limited parameters such as form factor (3U or 6U), interconnect topology, and number of slots in the backplane. For example, Elma Bustronic’s seven-slot OpenVPX Hybrid backplane (Fig. 4) has five VPX sockets interconnected using a full mesh with four serial interfaces per board.
This eliminates the need for a switch. The backplane has a pair of VME/64x slots as well, with the VME bus routed to the VPX connectors. The backplane references the BKP6-DIS05-11.2.16-1 profile. Assembly and deployment are now significantly easier when the backplane and boards used with the system comply with VITA 65.
The basic set of profiles lets designers and vendors work with new compatible hardware, but the base set is only the starting point. There will not be a flood of new designs, though they will be added as needed or as new architecture combinations become more popular.
Two of the new VITA specifications that will have an impact are VITA 66 (Fiber Optic Interconnect) and VITA 67 (coax Analog/RF Interconnect). Fiber and coax connections are common on the front panel. More connections are likely to move to the rear, though, as these standards come into play on the boards and backplanes. VITA 65 support will be critical here.
“OpenVPX: It’s all about the backplane,” says Ray Alderman, VITA executive director. In one sense, VITA 65 has brought back the commonality that VME had delivered in the past.
PARALLEL BACKPLANE IS HERE TO STAY
The military market is unlike the consumer and commercial markets, where technology turnover is measured in months or years. Military applications are measured in decades. This is one reason that parallel bus-based solutions like VME, CompactPCI, and even PC/104 are still found in new designs. These specifciations typically target the large replacement and upgrade market.
VXS attempts to bridge the gap between a full high-speed serial backplane like VPX and the parallel interface of VME. The challenge in the replacement and upgrade market is whether the backplane can be changed. If not, VXS boards still work, but their serial interface is wasted. Otherwise, designs open up a world of options.