Heterogeneous 2.5/3D Chip Design Requires Integrated Tools

June 3, 2024
Siemens’ Xpedition Substrate Integrator provides co-design prototyping and planning of 2.5/3D chips.

What you’ll learn:

  • Why co-optimization is needed when designing 2.5D and 3D chips.
  • The tools provided by Siemens for 2.5D and 3D chip design and packaging.


The latest high-performance chips often employ 2.5D and 3D chip technologies like chiplets to deliver their functionality within the required cost, power, and performance requirements. Companies are moving from system-based optimization to design-based optimization as system design and packaging become more complex.

I talked with Kevin Rinebold, Account Technology Manager for Advanced Packaging at Siemens EDA, about the changes in the industry, Siemens’ tools that address this space, and the company’s “cockpit.”

The workflow for 2.5/3D chip design requires quite a bit of planning and simulation to verify that a chip can be produced and meet the design requirements (Fig. 1). The process can be streamlined by using structured design frameworks such as assembly design kits (ADKs), package design kits (PDKs) and chip design kits (CDKs) that help design teams take advantage of specific chip fabrication technologies.

A more detailed flow diagram (Fig. 2) highlights the need for co-optimization between design, implementation, and verification. All of this is needed to make sure final chip production will be successful and the chips will meet their design requirements.

Siemens offers an integrated solution (Fig. 3) built around a single tool and system hierarchy to go from planning to prototyping and manufacturing. Among the tools in the mix are Xpedition design software, Calibre design verification, and SimCenter simulation and test platform. This includes chip and chiplet design at the RTL level through chip packaging. These tools can be used individually and with third-party tools.

The Siemens Xpedition Substrate Integrator is one of the tools available from Siemens; it addresses everything from mechanical design to chiplet and interposer design (Fig. 4). Product lifecycle management (PLM) and design for test (DFT) are part of the package, as is co-simulation support for thermal and mechanical aspects of the design.

About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

You can send press releases for new products for possible coverage on the website. I am also interested in receiving contributed articles for publishing on our website. Use our template and send to me along with a signed release form. 

Check out my blog, AltEmbedded on Electronic Design, as well as his latest articles on this site that are listed below. 

You can visit my social media via these links:

I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.  

I still get a hand on software and electronic hardware. Some of this can be found on our Kit Close-Up video series. You can also see me on many of our TechXchange Talk videos. I am interested in a range of projects from robotics to artificial intelligence. 

Sponsored Recommendations


To join the conversation, and become an exclusive member of Electronic Design, create an account today!