NVMe Controller Doubles Throughput for HPC Workloads
What you’ll learn:
- Features and performance of Marvell SC6 NVMe controller.
- Why support for faster storage is needed for data centers.
Flash memory is the mainstay for data center non-volatile storage as artificial intelligence (AI) continues to push the need for solutions with even higher bandwidth and capacity. NVMe has become the de facto standard, raising the importance of NVMe storage controllers.
I talked with Khurram Malik, Associate Vice President of Product Marketing at Marvell, (watch the video above) about the company’s latest NVMe controller, the Bravera SC6 (Fig. 1). It features Marvell’s 6th-generation NANDEdge technology that incorporates a low-density parity-check (LDPC) error correction engine. The controller is built to handle hyperscale data centers and high-performance computing (HPC) workloads.
The SC6 architecture is built around a compute engine that includes a dozen Arm Cortex-R82 cores and three Cortex-M7 cores (Fig. 2). The security subsystem is based on a Cortex-M3. The security system supports AES encryption, SHA hashing, RSA cryptography, and elliptic curve cryptography (ECC).
The chip includes 5 MB of on-chip SRAM, and the 64-bit DDR5 memory interface supports 8-bit ECC. It’s designed to match the performance of new, faster, and higher-capacity flash memory while providing higher throughput.
About the Author
William G. WongWilliam G. Wong
Senior Content Director - Electronic Design and Microwaves & RF
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.
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