In data centers, ultra-low on-resistance MOSFETs are core building blocks of the secondary-side synchronous-rectification stage in isolated DC-DC converters and ORing circuits used in server power supplies. These systems convert high-voltage AC into tightly regulated DC rails that power the hardware throughout the rack. Traditionally, the switches in the primary-side converter stage have been the biggest culprits when it comes to power losses, driving the adoption of silicon carbide (SiC) and gallium nitride (GaN) in those cases.

But as switching and conduction losses decline elsewhere in the power supply, the synchronous rectifier (SR) is emerging as another bottleneck.

At faster switching frequencies, the SR increasingly determines the system’s overall efficiency and how hard it is to manage the heat and electromagnetic interference (EMI). For that, Toshiba introduced the TPM1R408RH, an 80-V n-channel MOSFET based on its latest U-MOS11-H process that reduces both conduction and switching losses while tamping down EMI. 

Designed for densely packed AI data center racks and communications base stations, the FET features a more advanced device structure that reduces the drain-source on-resistance (R_DS(on)), the total gate charge (Q_G), and the usual tradeoff between them (R_DS(on) × Q_G). R_DS(on) and Q_G are two of the most important parameters for evaluating the efficiency of a power FET: the first determines conduction losses that occur when the device is on, while the second dictates the switching losses when turning the device on and off.

The device realizes a maximum on-resistance of 1.4 mΩ when operating from a 10-V gate-drive signal (V_GS). That’s approximately 26% less than that of TPM1R908QM, an 80-V MOSFET fabricated using Toshiba’s previous U-MOS X-H process.

Toshiba said it also improves the tradeoff between the R_DS(on) × Q_G, achieving approximately a 45% reduction in the figure of merit over the TPM1R908QM. Shrinking the R_DS(on) requires a larger silicon area, which inherently increases parasitic capacitance and Q_G. Conversely, minimizing Q_G for faster switching speeds usually sacrifices R_DS(on). According to the company, the characteristics of the TPM1R408RH result in new lows for power loss, both in terms of conduction and switching losses.

Consequently, the new device is particularly well-positioned for high-current power conversion in data centers, supporting a drain current of more than 280 A at a temperature of Tc = 25°C, said Toshiba.

The device is also inherently designed to suppress spike voltages generated between drain and source during switching, which helps reduce EMI in switching power supplies. EMI suppression is often left until late in the design cycle. But suppressing device-originated voltage spikes helps cut down on the rework in the late design stages. This also helps simplify snubber circuits commonly used to limit ringing and other noise, said Toshiba.

For additional power savings, the TPM1R408RH also leverages the company’s latest SOP Advance(E) package, which comes with approximately 65% lower package resistance and 15% lower thermal resistance than the existing SOP Advance(N) package, in a form factor of 4.9 × 6.1 × 1.0 mm. By suppressing more heat and dissipating whatever is unavoidable, the device can handle higher outputs while still enabling more compact power supply designs.