Node Wars: A Look Back at 2014, and Different Roads for 2015
Today’s Designs Require a Verification Continuum
Accelerate Design-Ins, Verification Via Virtual Lab Series
Q&A: An Interview with Kaufman Award Winner Dr. Lucio Lanza
Requiem for a Bug – Verifying Software, Part 2: Formal Verification through SPARK 2014
High-Level Synthesis Uncovers PPA Tradeoffs of Various Hardware Accelerators
Point/Counterpoint: Today’s FPGA Prototyping—Breaking the Typecast Mold
Point/Counterpoint: Hardware Emulation’s Versatility
Complex Chip Designs Need System-Level Scenario Coverage
Make the Move from Module-Based Mixed-Signal Verification to UVM