Electronic Design

Company Wire

Synopsys Inc. and Avant! Corp. have launched DesignSphere Access, located at www.designsphere.com. This open-hosted design environment reduces the cycle time and costs associated with taking designs from concept to silicon production. The environment also is linked to the Taiwan Semiconductor Manufacturing Company's (TSMC's) eFoundry service, offering a broad spectrum of functionality. It incorporates an array of EDA tools, computing resources, network capability, and security services, all accessible via the Internet.

Numetrics Management Systems Inc. and the Fabless Semiconductor Association are jointly working to measure the fabless semiconductor industry's design competitiveness. Numetrics' Design Productivity Management System benchmarks the chip-development capabilities of the fabless industry against the vertically integrated semiconductor industry and other chip-design organizations throughout the electronics industry. This information then can be used to help improve the fabless semiconductor industry's quality of work.

The Alba Center is working to demonstrate the potential for intellectual property (IP) evaluation via the Internet. Undertaken as part of the center's IP4EVAL Project, this effort will take advantage of Simultech's current technology. If proven viable, IP evaluation over the Internet will save design engineers time and money as they select components to populate their system-on-a-chip (SoC) designs.

Integrated Measurement Systems' Virtual Test Division has signed an agreement with Advantest America Inc. Advantest will ship IMS' Digital VirtualTester and TestDirect virtual test-software tools with every U.S. Advantest T6600 ultra-high-speed logic test system. The software will be bundled with each shipped tester. It also can be purchased as an option directly from Advantest. With this package, users get immediate access to software products to assist them in IC design verification and production test-program development.

Mentor Graphics Corp. has signed a non-exclusive licensing agreement with iRoC Technologies. Mentor will use iRoC's memory built-in self-test (BIST) technology for very deep-submicron ICs. The technology automatically generates an exact algorithm to fit the initial fault-model specification. This provides better memories while saving a significant amount of memory development time.

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