You've heard this before: The design of complex ASICs, application-specific standard products (ASSPs), and SoCs at the register-transfer level (RTL) is a dinosaur on its way to extinction. Electronic-system-level (ESL) design, an approach marked by early architectural exploration and true hardware/software co-design, has been anticipated—and under-delivered—by EDA vendors for years now. Taking multimillion-gate designs from an architectural specification to a gate-level netlist? Not in my lifetime, you're thinking. You're expecting to stick with tried-and-true RTL design using good old Verilog and VHDL. But will you? Think about it. The EDA industry has seen an upward shift in abstraction level in each of the last two decades. The 1980s saw a move from transistor level to gate level, while the 1990s were marked by the change from gates to RTL. The move to a still higher level of abstraction has been prognosticated ever since RTL came into broad usage. Surely, it was thought, by the time we'd gotten to 130-nm processes, there would simply be too much complexity to continue as we were. With too much silicon area available to be filled and not enough time to fill it using the traditional flow, RTL is at the breaking point and the "design gap" we see in so many PowerPoint presentations is real.
Over the past five years or so, the EDA industry has tried to keep the RTL flag flying. But it's time to face reality: The era of algorithm-centric design is upon us. The good news is that the design languages and tool flows to facilitate the shift to ESL design are finally coming together. In 2004, there will be even further coalescing of the tool flows, methodologies, and design and verification languages, nudging ESL even closer to the mainstream of IC design.
Filling those millions of gates at 90 and 65 nm will require a great deal more platform-based design, centering on embedded standard processors as well as custom processors. Software content will become a prime differentiator in the SoC age, which will in turn create new verification and simulation problems. Only by moving up in abstraction will the EDA industry be able to cope with the morass of modeling issues.
Designers must get over their distrust of timed and even untimed transaction-level modeling if there's any hope of sorting out the complex architectural tradeoffs. Recent advances in the bridging of various abstraction-level models have made simulation of mixed models much more viable. Expect more of the same in 2004 as new approaches to mixed-level modeling emerge.
The language wars are heating up again as different camps rally around their favored approaches. But language issues must be settled on a number of planes for ESL to really take off, particularly if platform-based approaches are to dominate. For one thing, we'll need a language that can be used for a higher-level specification of a complete system. That's best accomplished at this point with a language like the Universal Modeling Language (UML). At some point, perhaps Rosetta will be ready to take up the challenge it's been bred for. While UML hasn't yet made much of a dent in the hardware-design realm, Rosetta is on its way to Accellera standardization and should make further progress in 2004.
Modeling of a transaction-level system platform or a hardware/software environment is also required. One can argue that SystemC currently offers the greatest benefit, though others would say SystemVerilog has the necessary architectural and semantic features to shoulder the ESL load. SystemVerilog is more likely to be the bridge, forming a natural path from SystemC to implementation.
The verification challenges posed by nanometer design are further exacerbated because you're starting from a higher level of abstraction than RTL. A means of specifying design behavior that can be carried throughout the verification process is essential. Look for assertion-based verification (ABV) to gain significant ground in 2004, with many more designers getting on the ABV bandwagon. Assertions, along with a testbench language such as e or Vera, are a promising methodology for testbench automation. However, some believe that the testbench languages will eventually fall to the wayside as their slow execution speeds outweigh their advantages. SystemC and SystemVerilog will ultimately replace them as the best option for testbench creation.
There will also be increased emphasis on formal verification techniques, especially when it comes to ensuring that a block's RTL implementation meets the high-level requirements set at the architectural level. But formal verification won't make its big splash until assertions are fully accepted and firmly entrenched in verification methodologies.