Designing with Chiplets

The company rolled out Calibre 3D Thermal to help deliver fast and accurate die-level thermal analysis of 3D IC designs.

Learn how Ansys leverages NVIDIA’s Omniverse to unlock the future of 2.5D and 3D multi-die systems.

Mixing dies, interposers, and designs to fabricate new solutions.

Intel paired one of its CPUs with an optical compute interconnect (OCI) chiplet.

Discover how the Universal Memory Interface tackles substrate- and die-level real-estate challenges in chiplet-based design, unlocking performance and scalability.

The company’s next-gen AI silicon adds more accelerator cores, faster networking, and extra high-bandwidth memory.

Learn more about Pike Creek and its potential implications as the first test chip featuring chiplets linked by the UCIe standard.

When it comes to chiplets, it’s all about packaging technology.

Explore Keysight’s Chiplet PHY Designer tool and the game-changing UCIe standard in chip design.

The Chiplet Summit is coming up at the beginning of February. I hope to meet up with you there.

Intel’s latest data-center CPU is a prelude to the process and packaging innovations it has in store for 2024.

Jim Handy’s crystal ball reveals trends about many topics, ranging from memory chips to generative AI.

Explore the main driving forces behind today’s multi-die systems, how they’re becoming the choice system architecture, and how they’re catalyzing the next wave of semiconductor...

The Versal Premium adaptive System-on-Chip (SoC) targets EDA simulation and verification applications.

Intel’s Agilex 7 with R-Tile support works with PCIe 5.0 and CXL.

The recently announced Universal Chiplet Interconnect Express standard, based on PCIe and CXL, will help simplify chip design.

Chiplets – Electronic Design Automation Insights

zGlue’s ChipBuilder Pro lets designers create chips using its 2.5D chiplet Smart Fabric.

TSMC Works With Arm to Chart Future of Chiplets

Intel Adds New Technology to Advanced Packaging Arsenal

Intel Introduces New Way to Stack Chips on Top of Each Other

This silicon interposer fabric lets developers integrate multiple die into a single, compact chip. It is ideal for compact form factors needed for applications like wearable devices...