Electronic Design

EDA Roundup

BY BUILDING ON-CHIP VARIATION (OCV) analysis into its TimeCraft static-timing analysis tool, Incentia has given TimeCraft users a means of improving the accuracy and efficiency of static timing analysis. The tool's OCV engine enables users to address the effects of statistical process variation, which in turn permits them to eliminate excessive guardbanding. It's available for 32- and 64-bit Sun Solaris, Linux, and HP platforms. For more details, visit www.incentia.com.

ARITHMATICA AND SEQUENCE DESIGN have joined forces on low-power SoC design. Version 3.0 of Arithmatica's CellMath datapath tools incorporates power-knowledgeable synthesis and an extended Verilog interface that can specify robust datapath structures. Arithmatica is working with Sequence on RTL modeling at the gate level, so CellMath's results can be "power-certified" with Sequence's PowerTheatre tool. Visit www.sequencedesign.com.

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